| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 326 if (!STI.getFeatureBits().test(FeatureSupportsXNACK)) in AMDGPUTargetID()
328 if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC)) in AMDGPUTargetID()
518 if (STI->getFeatureBits().test(FeatureWavefrontSize16)) in getWavefrontSize()
520 if (STI->getFeatureBits().test(FeatureWavefrontSize32)) in getWavefrontSize()
527 if (STI->getFeatureBits().test(FeatureLocalMemorySize32768)) in getLocalMemorySize()
529 if (STI->getFeatureBits().test(FeatureLocalMemorySize65536)) in getLocalMemorySize()
539 if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode)) in getEUsPerCU()
612 if (STI->getFeatureBits().test(FeatureSGPRInitBug)) in getAddressableNumSGPRs()
634 if (STI->getFeatureBits().test(FeatureTrapHandler)) in getMinNumSGPRs()
651 if (STI->getFeatureBits().test(FeatureTrapHandler)) in getMaxNumSGPRs()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 174 if (!(getSTI().getFeatureBits()[Feature])) { in setFeatureBits()
181 bool getFeatureBits(uint64_t Feature) { in getFeatureBits() function in __anonb33428590111::RISCVAsmParser
182 return getSTI().getFeatureBits()[Feature]; in getFeatureBits()
186 if (getSTI().getFeatureBits()[Feature]) { in clearFeatureBits()
196 FeatureBitStack.push_back(getSTI().getFeatureBits()); in pushFeatureBits()
235 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); in RISCVAsmParser()
239 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { in RISCVAsmParser()
244 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { in RISCVAsmParser()
998 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); in MatchAndEmitInstruction()
1322 if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) { in parseCSRSystemRegister()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 48 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) in AMDGPUDisassembler()
434 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { in getInstruction()
464 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { in getInstruction()
473 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { in getInstruction()
495 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { in getInstruction()
501 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { in getInstruction()
512 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { in getInstruction()
565 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { in getInstruction()
637 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || in convertSDWAInst()
638 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { in convertSDWAInst()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.h | 38 STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName()); in RISCVAsmBackend()
39 RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits()); in RISCVAsmBackend()
49 return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax]; in willForceRelocations()
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| H A D | RISCVAsmBackend.cpp | 114 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; in shouldForceRelocation()
204 bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; in writeNopData()
420 if (!STI.getFeatureBits()[RISCV::FeatureRelax]) in shouldInsertExtraNopBytesForCodeAlign()
423 bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; in shouldInsertExtraNopBytesForCodeAlign()
443 if (!STI.getFeatureBits()[RISCV::FeatureRelax]) in shouldInsertFixupForCodeAlign()
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| H A D | RISCVMCCodeEmitter.cpp | 175 if (STI.getFeatureBits()[RISCV::FeatureRelax]) { in expandAddTPRel()
194 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
269 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; in getImmOpValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCInstPrinter.cpp | 69 return STI->getFeatureBits().test(C.Value); in matchAliasCondition()
71 return !STI->getFeatureBits().test(C.Value); in matchAliasCondition()
76 OrPredicateResult |= STI->getFeatureBits().test(C.Value); in matchAliasCondition()
80 OrPredicateResult |= !(STI->getFeatureBits().test(C.Value)); in matchAliasCondition()
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| H A D | MCInstrInfo.cpp | 21 STI.getFeatureBits()[DeprecatedFeatures[Opcode]]) { in getDeprecatedInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 135 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit16Encoding()
171 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit32Encoding()
207 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit64Encoding()
265 if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) in getLitEncoding()
304 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
340 if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) || in encodeInstruction()
341 (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])) in encodeInstruction()
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| H A D | AMDGPUMCAsmInfo.cpp | 63 if (STI->getFeatureBits()[AMDGPU::FeatureNSAEncoding]) in getMaxInstLength()
67 if (STI->getFeatureBits()[AMDGPU::FeatureVOP3Literal]) in getMaxInstLength()
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| H A D | R600MCCodeEmitter.cpp | 96 computeAvailableFeatures(STI.getFeatureBits())); in encodeInstruction()
108 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) { in encodeInstruction()
141 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) && in encodeInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMRCDeprecationInfo()
92 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
104 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMStoreDeprecationInfo()
120 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMLoadDeprecationInfo()
448 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; in isCDECoproc()
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| H A D | ARMAsmBackend.cpp | 209 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
210 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
604 (!STI->getFeatureBits()[ARM::FeatureThumb2] && in adjustFixupValue()
605 !STI->getFeatureBits()[ARM::HasV8MBaselineOps] && in adjustFixupValue()
606 !STI->getFeatureBits()[ARM::HasV6MOps] && in adjustFixupValue()
679 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { in adjustFixupValue()
704 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && in adjustFixupValue()
705 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { in adjustFixupValue()
716 if (!STI->getFeatureBits()[ARM::FeatureThumb2]) { in adjustFixupValue()
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| H A D | ARMAsmBackend.h | 38 bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; } in hasNOP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVSubtarget.cpp | 71 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); in initializeSubtargetDependencies()
72 RISCVFeatures::validate(TT, getFeatureBits()); in initializeSubtargetDependencies()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyTargetTransformInfo.cpp | 109 TM.getSubtargetImpl(*Caller)->getFeatureBits(); in areInlineCompatible()
111 TM.getSubtargetImpl(*Callee)->getFeatureBits(); in areInlineCompatible()
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| H A D | WebAssemblyTargetMachine.cpp | 230 ->getFeatureBits(); in coalesceFeatures()
232 Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits(); in coalesceFeatures()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 338 if (STI->getFeatureBits()[F]) in clearFeature()
343 return STI->getFeatureBits()[F]; in checkFeature()
498 llvm::FeatureBitset Features = X->getFeatureBits(); in createHexagonMCSubtargetInfo()
502 X->setFeatureBits(completeHVXFeatures(X->getFeatureBits())); in createHexagonMCSubtargetInfo()
510 llvm::FeatureBitset Features = X->getFeatureBits(); in createHexagonMCSubtargetInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 67 .getFeatureBits(); in DecodeGPRRegisterClass()
440 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { in getInstruction()
452 if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] && in getInstruction()
453 STI.getFeatureBits()[RISCV::FeatureStdExtC]) { in getInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 868 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
870 if (STI.getFeatureBits()[X86::FeatureAVX]) in setRegTo()
875 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
877 if (STI.getFeatureBits()[X86::FeatureAVX]) in setRegTo()
881 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
894 STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR : X86::LDMXCSR, in setRegTo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 474 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch()
479 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in selectArch()
483 if (!(getSTI().getFeatureBits()[Feature])) { in setFeatureBits()
487 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in setFeatureBits()
492 if (getSTI().getFeatureBits()[Feature]) { in clearFeatureBits()
496 AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); in clearFeatureBits()
502 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); in setModuleFeatureBits()
507 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits()); in clearModuleFeatureBits()
540 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); in MipsAsmParser()
544 std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits())); in MipsAsmParser()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 176 STI.getFeatureBits()[AArch64::HasV8_2aOps]) { in printInst()
803 if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits())) in printSysAlias()
820 if (!IC || !IC->haveFeatures(STI.getFeatureBits())) in printSysAlias()
832 if (!DC || !DC->haveFeatures(STI.getFeatureBits())) in printSysAlias()
843 if (!AT || !AT->haveFeatures(STI.getFeatureBits())) in printSysAlias()
855 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) in printSysAlias()
1460 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) in printMRSSystemRegister()
1486 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) in printMSRSystemRegister()
1498 if (PState && PState->haveFeatures(STI.getFeatureBits())) in printSystemPStateField()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 842 bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit]; in relaxInstruction()
861 bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit]; in isFullyRelaxed()
1089 if (STI.getFeatureBits()[X86::FeatureFast7ByteNOP]) in getMaximumNopSize()
1091 if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP]) in getMaximumNopSize()
1093 if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP]) in getMaximumNopSize()
1141 STI.getFeatureBits()[X86::Mode16Bit] ? Nops16Bit : Nops32Bit; in writeNopData()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRELFStreamer.cpp | 63 EFlags |= getEFlagsForFeatureSet(STI.getFeatureBits()); in AVRELFStreamer()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), in MipsDisassembler()
50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } in hasMips2()
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } in hasMips3()
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } in hasMips32()
55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; in hasMips32r6()
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } in isFP64()
60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } in isGP64()
62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } in isPTR64()
64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } in hasCnMips()
66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } in hasCnMipsP()
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