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Searched refs:dpm_level (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Drenoir_ppt.h35 #define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq) \ argument
39 freq = table->SocClocks[dpm_level].Freq; \
42 freq = table->MemClocks[dpm_level].Freq; \
45 freq = table->DcfClocks[dpm_level].Freq; \
48 freq = table->FClocks[dpm_level].Freq; \
H A Damdgpu_amd_powerplay.c324 if (!(hwmgr->dpm_level & profile_mode_mask)) { in pp_dpm_en_umd_pstate()
327 hwmgr->saved_dpm_level = hwmgr->dpm_level; in pp_dpm_en_umd_pstate()
360 if (level == hwmgr->dpm_level) in pp_dpm_force_performance_level()
382 level = hwmgr->dpm_level; in pp_dpm_get_performance_level()
733 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_dpm_force_clock_level()
907 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in pp_set_power_profile_mode()
989 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in pp_dpm_switch_power_profile()
H A Damdgpu_smu.c816 smu->smu_dpm.dpm_level, in smu_late_init()
933 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in smu_sw_init()
1686 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { in smu_enable_umd_pstate()
1689 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; in smu_enable_umd_pstate()
1750 if (smu_dpm_ctx->dpm_level != level) { in smu_adjust_power_state_dynamic()
1758 smu_dpm_ctx->dpm_level = level; in smu_adjust_power_state_dynamic()
1761 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_adjust_power_state_dynamic()
1836 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) in smu_switch_power_profile()
1853 level = smu_dpm_ctx->dpm_level; in smu_get_performance_level()
1903 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in smu_force_clk_levels()
H A Dsmu_internal.h200 #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) \ argument
201 …clk_limited ? (smu)->ppt_funcs->get_dpm_clk_limited((smu), (clk_type), (dpm_level), (freq)) : -EIN…
H A Damdgpu_vega20_ppt.c2115 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega20_apply_clocks_adjust_rules()
2120 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2137 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega20_apply_clocks_adjust_rules()
2142 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2179 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2196 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2213 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2230 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
2588 ret = smu_handle_task(smu, smu_dpm->dpm_level, in vega20_set_od_percentage()
2816 ret = smu_handle_task(smu, smu_dpm->dpm_level, in vega20_odn_edit_dpm_table()
H A Damdgpu_renoir_ppt.c231 uint32_t dpm_level, uint32_t *freq) in renoir_get_dpm_clk_limited() argument
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); in renoir_get_dpm_clk_limited()
H A Damdgpu_navi10_ppt.c2147 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level, in navi10_od_edit_dpm_table()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu_helper.c360 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
371 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
372 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
373 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
384 if (dpm_table->dpm_level[i - 1].enabled) in phm_get_dpm_level_enable_mask_value()
455 if (value == dpm_table->dpm_level[i].value) { in phm_find_boot_level()
H A Damdgpu_pp_psm.c288 hwmgr->dpm_level = hwmgr->request_dpm_level; in psm_adjust_power_state_dynamic()
290 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { in psm_adjust_power_state_dynamic()
H A Damdgpu_vega12_hwmgr.c2202 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega12_apply_clocks_adjust_rules()
2207 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2226 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega12_apply_clocks_adjust_rules()
2231 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2270 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2289 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2308 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
2327 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega12_apply_clocks_adjust_rules()
H A Dppatomctrl.h316 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
H A Damdgpu_vega20_hwmgr.c3666 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { in vega20_apply_clocks_adjust_rules()
3671 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3690 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { in vega20_apply_clocks_adjust_rules()
3695 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3750 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3769 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3788 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
3807 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { in vega20_apply_clocks_adjust_rules()
H A Damdgpu_hwmgr.c97 hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; in hwmgr_early_init()
H A Damdgpu_ppatomctrl.c651 uint16_t dpm_level, in atomctrl_calculate_voltage_evv_on_sclk() argument
700 switch (dpm_level) { in atomctrl_calculate_voltage_evv_on_sclk()
H A Damdgpu_vega10_hwmgr.c4242 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE… in vega10_dpm_force_dpm_level()
4244 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR… in vega10_dpm_force_dpm_level()
4555 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) in vega10_print_clock_levels()
H A Damdgpu_smu7_hwmgr.c2848 …if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE… in smu7_force_dpm_level()
2850 …else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PR… in smu7_force_dpm_level()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Damdgpu_smu.h286 enum amd_dpm_forced_level dpm_level; member
487 uint32_t dpm_level, uint32_t *freq);
H A Dhwmgr.h65 struct vi_dpm_level dpm_level[1]; member
760 enum amd_dpm_forced_level dpm_level; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_ci_smumgr.c2886 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM)) in ci_update_uvd_smc_table()
2917 if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM)) in ci_update_vce_smc_table()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pm.c3506 smu_dpm->dpm_level, in amdgpu_pm_compute_clocks()