Searched refs:dm_write_reg_soc15 (Results 1 – 2 of 2) sorted by relevance
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| H A D | amdgpu_dce120_timing_generator.c | 266 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0); in dce120_timing_generator_setup_global_swap_lock()
429 dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value); in dce120_timing_generator_disable_vga()
523 dm_write_reg_soc15( in dce120_timing_generator_set_overscan_color_black()
533 dm_write_reg_soc15( in dce120_timing_generator_set_overscan_color_black()
701 dm_write_reg_soc15(tg->ctx, in dce120_timing_generator_enable_advanced_request()
723 dm_write_reg_soc15( in dce120_tg_program_blank_color()
790 dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL, in dce120_tg_set_blank()
951 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0); in dce120_timing_generator_set_test_pattern()
990 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value); in dce120_timing_generator_set_test_pattern()
1003 dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value); in dce120_timing_generator_set_test_pattern()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dm_services.h | 171 #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ macro
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