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Searched refs:dm_read_reg_soc15 (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_timing_generator.c95 uint32_t value = dm_read_reg_soc15( in dce120_timing_generator_is_in_vertical_blank()
178 uint32_t value = dm_read_reg_soc15( in dce120_timing_generator_get_vblank_counter()
194 uint32_t value = dm_read_reg_soc15( in dce120_timing_generator_get_crtc_position()
205 value = dm_read_reg_soc15( in dce120_timing_generator_get_crtc_position()
256 dm_read_reg_soc15(tg->ctx, in dce120_timing_generator_setup_global_swap_lock()
317 uint32_t pol_value = dm_read_reg_soc15( in dce120_timing_generator_enable_reset_trigger()
379 uint32_t value = dm_read_reg_soc15( in dce120_timing_generator_did_triggered_reset_occur()
421 value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset); in dce120_timing_generator_disable_vga()
518 value = dm_read_reg_soc15( in dce120_timing_generator_set_overscan_color_black()
613 value = dm_read_reg_soc15( in dce120_timing_generator_get_position()
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H A Damdgpu_dce120_resource.c667 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); in read_dce_straps()
676 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); in read_dce_straps()
1026 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); in read_pipe_fuses()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services.h174 #define dm_read_reg_soc15(ctx, reg, inst_offset) \ macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_resource.c1309 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); in read_pipe_fuses()