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Searched refs:dm_read_reg (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_compressor.c88 status_pos = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION)); in reset_lb_on_vblank()
92 if (status_pos != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_POSITION))) { in reset_lb_on_vblank()
94 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); in reset_lb_on_vblank()
99 frame_count = dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT)); in reset_lb_on_vblank()
103 if (frame_count != dm_read_reg(compressor->ctx, DCP_REG(mmCRTC_STATUS_FRAME_COUNT))) in reset_lb_on_vblank()
111 value = dm_read_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL)); in reset_lb_on_vblank()
127 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
153 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
168 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
175 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
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H A Damdgpu_dce110_mem_input_v.c50 value = dm_read_reg( in set_flip_control()
163 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); in enable()
376 value = dm_read_reg( in program_pixel_format()
428 value = dm_read_reg( in program_pixel_format()
448 value = dm_read_reg( in program_pixel_format()
482 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE); in dce_mem_input_v_is_surface_pending()
613 value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT); in dce_mem_input_v_program_pte_vm()
619 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL); in dce_mem_input_v_program_pte_vm()
625 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL); in dce_mem_input_v_program_pte_vm()
630 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C); in dce_mem_input_v_program_pte_vm()
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H A Damdgpu_dce110_timing_generator_v.c90 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
108 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
128 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_unblank_crtc()
153 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_is_in_vertical_blank()
166 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); in dce110_timing_generator_v_is_counter_moving()
178 value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION); in dce110_timing_generator_v_is_counter_moving()
265 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
274 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
283 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
306 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
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H A Damdgpu_dce110_timing_generator.c105 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
118 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
162 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color()
204 value = dm_read_reg(tg->ctx, addr);
267 regval = dm_read_reg(tg->ctx, in program_horz_count_by_2()
384 v_total_min = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
387 v_total_max = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
390 v_total_cntl = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_drr()
489 static_screen_cntl = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_set_static_screen_control()
522 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_get_vblank_counter()
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H A Damdgpu_dce110_opp_regamma_v.c44 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
78 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
95 value = dm_read_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
528 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in dce110_opp_power_on_regamma_lut_v()
H A Damdgpu_dce110_opp_csc_v.c119 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); in program_color_matrix_v()
371 uint32_t value = dm_read_reg(ctx, addr); in configure_graphics_mode_v()
470 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); in set_Denormalization()
560 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL); in program_input_csc()
H A Damdgpu_dce110_transform_v.c285 value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); in set_coeff_update_complete()
309 power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL); in program_multi_taps_filter()
317 dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS), in program_multi_taps_filter()
516 value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); in dce110_xfmv_power_up_line_buffer()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_compressor.c307 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
330 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
345 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
352 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
399 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_enable_fbc()
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_disable_fbc()
454 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); in dce112_compressor_is_fbc_enabled_in_hw()
461 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce112_compressor_is_fbc_enabled_in_hw()
463 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_is_fbc_enabled_in_hw()
478 uint32_t value = dm_read_reg(compressor->ctx, in dce112_compressor_is_lpt_enabled_in_hw()
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H A Damdgpu_dce112_hw_sequencer.c82 value = dm_read_reg(ctx, addr); in dce112_init_pte()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Damdgpu_dc_helper.c270 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
334 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get()
343 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get2()
354 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get3()
367 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get4()
382 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get5()
399 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get6()
418 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get7()
439 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get8()
513 reg_val = dm_read_reg(ctx, addr); in generic_reg_wait()
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H A Ddm_services.h67 #define dm_read_reg(ctx, address) \ macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/
H A Damdgpu_irq_service.c100 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_set_generic()
137 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_ack_generic()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
H A Damdgpu_dce80_timing_generator.c97 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
135 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
H A Damdgpu_irq_service_dce80.c52 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
61 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
H A Damdgpu_irq_service_dce120.c52 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
61 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
H A Damdgpu_irq_service_dcn20.c133 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
142 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
H A Damdgpu_irq_service_dcn10.c133 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
142 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
H A Damdgpu_irq_service_dcn21.c134 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
143 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c53 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
60 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_link_encoder.c503 uint32_t value = dm_read_reg(ctx, addr); in aux_initialize()
510 value = dm_read_reg(ctx, addr); in aux_initialize()
1380 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_enable_hpd()
1393 uint32_t value = dm_read_reg(ctx, addr); in dce110_link_encoder_disable_hpd()
H A Damdgpu_dce_dmcu.c882 psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58); in dcn21_dmcu_construct()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_hw_sequencer.c118 value = dm_read_reg(ctx, addr);
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_link_encoder.c272 dm_read_reg(CTX, AUX_REG(reg_name))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_link_encoder.c1346 dm_read_reg(CTX, HPD_REG(reg_name))
1378 dm_read_reg(CTX, AUX_REG(reg_name))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
H A Dreg_helper.h42 dm_read_reg(CTX, REG(reg_name))

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