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Searched refs:dce_environment (Results 1 – 25 of 36) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Damdgpu_hw_translate.c66 enum dce_environment dce_environment) in dal_hw_translate_init() argument
68 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_translate_init()
H A Damdgpu_hw_factory.c68 enum dce_environment dce_environment) in dal_hw_factory_init() argument
70 if (IS_FPGA_MAXIMUS_DC(dce_environment)) { in dal_hw_factory_init()
H A Dhw_translate.h50 enum dce_environment dce_environment);
H A Dhw_factory.h77 enum dce_environment dce_environment);
H A Damdgpu_gpio_service.c62 enum dce_environment dce_version_minor, in dal_gpio_service_create()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_types.h57 enum dce_environment { enum
74 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ argument
75 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
77 #define IS_DIAG_DC(dce_environment) \ argument
78 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
106 enum dce_environment dce_environment; member
H A Ddc.h564 enum dce_environment dce_environment; member
H A Damdgpu_dc_helper.c519 !IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
531 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in generic_reg_wait()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_link_hwss.c406 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dp_set_dsc_on_rx()
455 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
480 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_on_stream()
545 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_pps_sdp()
554 if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dp_set_dsc_pps_sdp()
H A Damdgpu_dc_stream.c419 if (IS_DIAG_DC(dc->ctx->dce_environment)) { in dc_stream_add_writeback()
485 if (IS_DIAG_DC(dc->ctx->dce_environment)) { in dc_stream_remove_writeback()
H A Damdgpu_dc.c605 dc_ctx->dce_environment = init_params->dce_environment; in dc_construct_ctx()
714 dc_ctx->dce_environment, in dc_construct()
845 if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) { in dc_create()
894 if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) in dc_hardware_init()
2200 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { in commit_planes_for_stream()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
H A Damdgpu_dce112_clk_mgr.c118 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_clock()
160 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dce112_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_resource.c1361 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) in update_bw_bounding_box()
1410 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) { in dcn21_pp_smu_create()
1677 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) in dcn21_resource_construct()
1704 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) in dcn21_resource_construct()
1706 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { in dcn21_resource_construct()
1905 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn21_resource_construct()
H A Damdgpu_dcn21_init.c143 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn21_hw_sequencer_construct()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Damdgpu_rv1_clk_mgr_vbios_smu.c108 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rv1_vbios_smu_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/include/
H A Dgpio_service_interface.h48 enum dce_environment dce_version_minor,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
H A Damdgpu_dce112_hw_sequencer.c128 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce112_enable_display_power_gating()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr_vbios_smu.c99 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in rn_vbios_smu_set_dispclk()
H A Damdgpu_rn_clk_mgr.c160 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { in rn_update_clocks()
723 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in rn_clk_mgr_construct()
758 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { in rn_clk_mgr_construct()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_init.c134 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn20_hw_sequencer_construct()
H A Damdgpu_dcn20_optc.c338 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) in optc2_triplebuffer_lock()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_hw_sequencer.c167 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) in dce120_enable_display_power_gating()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hw_sequencer.c875 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_reset_back_end_for_pipe()
1255 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()
1284 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_init_hw()
2654 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_prepare_bandwidth()
2687 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { in dcn10_optimize_bandwidth()
H A Damdgpu_dcn10_resource.c1360 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) in dcn10_resource_construct()
1586 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? in dcn10_resource_construct()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c456 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { in dcn20_clk_mgr_construct()

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