| /netbsd-src/usr.bin/make/unit-tests/ |
| H A D | dotwait.mk | 5 TESTS= simple recursive shared cycle
58 cycle: cycle.1.99 .WAIT cycle.2.99
59 cycle.2.99: cycle.2.98 _ECHOUSE
60 cycle.2.98: cycle.2.97 _ECHOUSE
61 cycle.2.97: cycle.2.99 _ECHOUSE
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| /netbsd-src/external/gpl3/binutils.old/dist/include/opcode/ |
| H A D | tic6x-opcode-table.h | 132 INSN(abs, l, unary, 1cycle, C62X, 0,
137 INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
142 INSN(abs2, l, unary, 1cycle, C64X, 0,
154 INSN(abssp, s, unary, 1cycle, C67X, 0,
160 INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
165 INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
170 INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
175 INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
180 INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
185 INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
[all …]
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| /netbsd-src/external/gpl3/binutils/dist/include/opcode/ |
| H A D | tic6x-opcode-table.h | 132 INSN(abs, l, unary, 1cycle, C62X, 0,
137 INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
142 INSN(abs2, l, unary, 1cycle, C64X, 0,
154 INSN(abssp, s, unary, 1cycle, C67X, 0,
160 INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
165 INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
170 INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
175 INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
180 INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
185 INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ScoreboardHazardRecognizer.cpp | 118 int cycle = Stalls; in getHazardType() local
135 int StageCycle = cycle + (int)i; in getHazardType()
166 cycle += IS->getNextCycles(); in getHazardType()
185 unsigned cycle = 0; in EmitInstruction() local
194 assert(((cycle + i) < RequiredScoreboard.getDepth()) && in EmitInstruction()
201 freeUnits &= ~ReservedScoreboard[cycle + i]; in EmitInstruction()
205 freeUnits &= ~RequiredScoreboard[cycle + i]; in EmitInstruction()
217 RequiredScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
219 ReservedScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
223 cycle += IS->getNextCycles(); in EmitInstruction()
|
| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/cris/asm/ |
| H A D | tmvmrv10.ms | 14 ; Check that movem to register basically looks ok cycle-wise.
27 test.d [r3] ; 3 cycle penalty on v32 (2 memory source, 1 movem dest).
30 test.d [r3] ; 2 cycle penalty on v32.
32 subq 1,r1 ; 3 cycle penalty on v32.
35 subq 1,r1 ; 2 cycle penalty on v32.
39 subq 1, r1 ; 1 cycle penalty on v32.
|
| /netbsd-src/external/gpl3/binutils/dist/gprof/ |
| H A D | bsd_callg_bl.m | 31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
|
| H A D | fsf_callg_bl.m | 32 cycle, the cycle number is printed between the
51 member of a cycle, the cycle number is printed between
73 member of a cycle, the cycle number is printed
77 entry for the cycle-as-a-whole. This entry shows who called the
78 cycle (as parents) and the members of the cycle (as children.)
80 were internal to the cycle, and the calls entry for each member shows,
82 the cycle.
|
| /netbsd-src/external/gpl3/binutils.old/dist/gprof/ |
| H A D | bsd_callg_bl.m | 31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
|
| H A D | fsf_callg_bl.m | 32 cycle, the cycle number is printed between the
51 member of a cycle, the cycle number is printed between
73 member of a cycle, the cycle number is printed
77 entry for the cycle-as-a-whole. This entry shows who called the
78 cycle (as parents) and the members of the cycle (as children.)
80 were internal to the cycle, and the calls entry for each member shows,
82 the cycle.
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/mips/ |
| H A D | sb1.md | 25 ;; each cycle.
39 ;; insn can issue per cycle (fp1).
63 ;; DMULT block any multiply from issuing in the next cycle.
86 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
88 ;; can have at most 4 long-cycle operations per pipe.
114 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not
115 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8
116 ;; cycle ifetch bubble. We assume all branches predicted not taken.
126 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
134 ;; insns can be issued in the same cycle. However, a value of 1 gives
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mips/ |
| H A D | sb1.md | 25 ;; each cycle.
39 ;; insn can issue per cycle (fp1).
63 ;; DMULT block any multiply from issuing in the next cycle.
86 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
88 ;; can have at most 4 long-cycle operations per pipe.
114 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not
115 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8
116 ;; cycle ifetch bubble. We assume all branches predicted not taken.
126 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
134 ;; insns can be issued in the same cycle. However, a value of 1 gives
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/ |
| H A D | mcf.c | 785 int *pi, gcov_type *d, int *cycle) in cancel_negative_cycle() argument
808 cycle[i] = -1; in cancel_negative_cycle()
858 cycle[0] = pfedge->dest; in cancel_negative_cycle()
864 cycle[i] = j; in cancel_negative_cycle()
867 if (cycle[k] == j) in cancel_negative_cycle()
880 gcc_assert (cycle[cycle_start] == cycle[cycle_end]); in cancel_negative_cycle()
889 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
893 fprintf (dump_file, "%d ", cycle[k]); in cancel_negative_cycle()
898 fprintf (dump_file, "%d", cycle[k]); in cancel_negative_cycle()
909 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | mcf.cc | 785 int *pi, gcov_type *d, int *cycle) in cancel_negative_cycle() argument
808 cycle[i] = -1; in cancel_negative_cycle()
858 cycle[0] = pfedge->dest; in cancel_negative_cycle()
864 cycle[i] = j; in cancel_negative_cycle()
867 if (cycle[k] == j) in cancel_negative_cycle()
880 gcc_assert (cycle[cycle_start] == cycle[cycle_end]); in cancel_negative_cycle()
889 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
893 fprintf (dump_file, "%d ", cycle[k]); in cancel_negative_cycle()
898 fprintf (dump_file, "%d", cycle[k]); in cancel_negative_cycle()
909 pfedge = find_fixup_edge (fixup_graph, cycle[k + 1], cycle[k]); in cancel_negative_cycle()
[all …]
|
| /netbsd-src/lib/libmenu/ |
| H A D | internals.c | 91 int neighbour, cycle, row_major, edge; in _menui_calc_neighbours() local
95 cycle = ((menu->opts & O_NONCYCLIC) != O_NONCYCLIC); in _menui_calc_neighbours()
99 if (cycle) { in _menui_calc_neighbours()
111 if (cycle) in _menui_calc_neighbours()
143 if ((!cycle) && (edge == 1)) in _menui_calc_neighbours()
150 if (cycle) in _menui_calc_neighbours()
184 if ((!cycle) && (edge == 1)) in _menui_calc_neighbours()
190 if (cycle) { in _menui_calc_neighbours()
201 if (cycle) in _menui_calc_neighbours()
230 if ((!cycle) && (edge == 1)) in _menui_calc_neighbours()
[all …]
|
| /netbsd-src/external/lgpl3/gmp/dist/mpn/ia64/ |
| H A D | README | 56 execute two bundles per cycle. The Itanium 1 allows 4 of these instructions
73 * At most four integer instructions/cycle.
146 read rp[] to integer registers, allowing for just one getf.sig per cycle.
157 the 4 cycle latency of xma, this means we need at least 3 blocks. Using
175 recurrencies (1 cycle) but the sequence takes up 4 execution slots. When
176 recurrency depth is not critical, a more standard 3-cycle add+cmp+add is
223 49 insn at max 6 insn/cycle: 8.167 cycles/limb8
224 11 memops at max 2 memops/cycle: 5.5 cycles/limb8
225 16 fpops at max 2 fpops/cycle: 8 cycles/limb8
226 21 intops at max 4 intops/cycle: 5.25 cycles/limb8
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/ |
| H A D | cortex-a9-neon.md | 239 ;; Only one instruction can be issued per cycle.
242 ;; Only one data-processing instruction can be issued per cycle.
248 ;; E2 of the floating-point add pipeline. On the cycle previous to that
258 ;; We assume that multi-cycle NEON instructions get decomposed into
391 ;; produce a result at N6 on cycle 2.
398 ;; produce a result at N3 on cycle 2.
412 ;; produce a result at N6 on cycle 2.
419 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
435 ;; produce a result at N6 on cycle 2.
443 ;; produce a result at N6 on cycle 2.
[all …]
|
| H A D | cortex-a8-neon.md | 240 ;; per cycle.
243 ;; Only one data-processing instruction can be issued per cycle.
252 ;; E2 of the floating-point add pipeline. On the cycle previous to that
260 ;; We assume that multi-cycle NEON instructions get decomposed into
263 ;; upon the first and last cycles of a multi-cycle instruction, but it
264 ;; is unclear whether two multi-cycle instructions can issue together (in
266 ;; a multi-cycle and single-cycle instructions, that could potentially
267 ;; issue together, only do so if (say) the single-cycle one precedes
474 ;; produce a result at N6 on cycle 2.
481 ;; produce a result at N3 on cycle 2.
[all …]
|
| H A D | arm1020e.md | 88 ;; the shift value in a second cycle. Pretend we take two cycles in
141 ;; cycle in which both words are available.
144 ;; three iterations through the execute cycle, and make their results
145 ;; available after the memory cycle.
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
194 ;; base address is 64-bit aligned; if it is not, an additional cycle
196 ;; aligned. Because the processor can load two registers per cycle,
200 ;; The ALU pipeline is decoupled after the first cycle unless there is
280 ;; first execute state. We model this by using 1020a_e in the first cycle.
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/ |
| H A D | cortex-a9-neon.md | 239 ;; Only one instruction can be issued per cycle.
242 ;; Only one data-processing instruction can be issued per cycle.
248 ;; E2 of the floating-point add pipeline. On the cycle previous to that
258 ;; We assume that multi-cycle NEON instructions get decomposed into
391 ;; produce a result at N6 on cycle 2.
398 ;; produce a result at N3 on cycle 2.
412 ;; produce a result at N6 on cycle 2.
419 ;; their (D|Q)m operands at N1, and produce a result at N6 on cycle 2.
435 ;; produce a result at N6 on cycle 2.
443 ;; produce a result at N6 on cycle 2.
[all …]
|
| H A D | cortex-a8-neon.md | 240 ;; per cycle.
243 ;; Only one data-processing instruction can be issued per cycle.
252 ;; E2 of the floating-point add pipeline. On the cycle previous to that
260 ;; We assume that multi-cycle NEON instructions get decomposed into
263 ;; upon the first and last cycles of a multi-cycle instruction, but it
264 ;; is unclear whether two multi-cycle instructions can issue together (in
266 ;; a multi-cycle and single-cycle instructions, that could potentially
267 ;; issue together, only do so if (say) the single-cycle one precedes
474 ;; produce a result at N6 on cycle 2.
481 ;; produce a result at N3 on cycle 2.
[all …]
|
| H A D | arm1020e.md | 88 ;; the shift value in a second cycle. Pretend we take two cycles in
141 ;; cycle in which both words are available.
144 ;; three iterations through the execute cycle, and make their results
145 ;; available after the memory cycle.
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
174 ;; with LSL of zero. The remainder take 1 cycle to execute.
194 ;; base address is 64-bit aligned; if it is not, an additional cycle
196 ;; aligned. Because the processor can load two registers per cycle,
200 ;; The ALU pipeline is decoupled after the first cycle unless there is
280 ;; first execute state. We model this by using 1020a_e in the first cycle.
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP7.td | 46 // Each LSU pipeline can complete a load or store in one cycle.
51 // FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
52 // VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
54 // Frequent FX ops. take only one cycle and results can be used again in the
55 // next cycle (there is a self-bypass). Getting results from the other FX
56 // pipeline takes an additional cycle.
61 // (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
69 // share the same write-back, and have a 5-cycle latency difference, so the
387 let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
390 // cycle (from all queues) is 8.
|
| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | omap3430-sdp.dts | 73 gpmc,rd-cycle-ns = <186>;
74 gpmc,wr-cycle-ns = <186>;
123 gpmc,rd-cycle-ns = <72>;
124 gpmc,wr-cycle-ns = <72>;
169 gpmc,rd-cycle-ns = <108>;
170 gpmc,wr-cycle-ns = <96>;
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| H A D | power10.md | 57 ; Power10 can dispatch a maximum of 8 iops per cycle. With a maximum of
58 ; 4 VSU/2 Load/2 Store per cycle.
70 ; 4-way cracked (consumes whole decode/dispatch cycle)
197 ; Update forms have 2 cycle latency for updated addr reg
247 ; Most ALU insns are simple 2 cycle, including record form
253 ; 4 cycle CR latency
282 ; 5 cycle CR latency
290 ; 5 cycle CR latency
315 ; 4 cycle MUL->MUL latency
324 ; 4 cycle MUL->MUL latency
[all …]
|
| /netbsd-src/external/lgpl3/gmp/dist/mpn/alpha/ |
| H A D | README | 82 of one each 21st cycle.
87 L1 cache can handle two loads or one store per cycle, but two cycles after a
90 2. mulq has a latency of 12 cycles and an issue rate of 1 each 8th cycle.
91 umulh has a latency of 14 cycles and an issue rate of 1 each 10th cycle.
113 a cmoveq/cmovne, which could issue one cycle earlier that the `or', but that
114 might waste a cycle on EV4. The total depth remain unaffected, since cmov
126 cycle per limb, or bring us down to a total of 17 cycles or 4.25 cycles/limb.
141 instructions per cycle. In actual practice, it is never possible to sustain
142 more than 3.5 integer insns/cycle due to rename register shortage. One integer
143 multiply instruction can issue each cycle. To get optimal speed, we need to
[all …]
|