Searched refs:ctrl1 (Results 1 – 7 of 7) sorted by relevance
1004 val |= pll->state.hw_state.ctrl1 << (id * 6); in skl_ddi_pll_write_ctrl1()1076 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()1114 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()1372 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local1379 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_hdmi_pll_dividers()1381 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); in skl_ddi_hdmi_pll_dividers()1400 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()1409 u32 ctrl1; in skl_ddi_dp_set_dpll_hw_state() local1415 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_dp_set_dpll_hw_state()1418 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); in skl_ddi_dp_set_dpll_hw_state()[all …]
188 u32 ctrl1; member
1636 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { in skl_ddi_clock_get()1639 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); in skl_ddi_clock_get()
13673 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); in intel_pipe_config_compare()
460 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
767 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
132 uint32_t ctrl1;125 uint32_t ctrl1; global() member