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Searched refs:clear_state_gpu_addr (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_rlc.c140 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
272 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
H A Damdgpu_rlc.h142 uint64_t clear_state_gpu_addr; member
H A Damdgpu_gfx_v6_0.c2412 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2422 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2834 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2941 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2949 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
H A Damdgpu_gfx_v7_0.c3895 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3896 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4545 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
H A Damdgpu_gfx_v10_0.c1001 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
1794 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
1796 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
H A Damdgpu_gfx_v8_0.c2086 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v8_0_sw_fini()
3897 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v8_0_init_csb()
3899 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v8_0_init_csb()
H A Damdgpu_gfx_v9_0.c2578 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v9_0_init_csb()
2580 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v9_0_init_csb()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_evergreen.c4272 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4291 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4298 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4418 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
H A Dradeon_si.c5296 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5793 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5799 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
H A Dradeon.h1041 uint64_t clear_state_gpu_addr; member
H A Dradeon_cik.c6646 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6647 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()