| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| H A D | intel_timeline.c | 56 hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline) in hwsp_alloc() argument
94 *cacheline = __ffs64(hwsp->free_bitmap); in hwsp_alloc()
95 hwsp->free_bitmap &= ~BIT_ULL(*cacheline); in hwsp_alloc()
105 static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline) in __idle_hwsp_free() argument
116 GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap)); in __idle_hwsp_free()
117 hwsp->free_bitmap |= BIT_ULL(cacheline); in __idle_hwsp_free()
162 cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline) in cacheline_alloc() argument
167 GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS)); in cacheline_alloc()
181 cl->vaddr = page_pack_bits(vaddr, cacheline); in cacheline_alloc()
225 unsigned int cacheline; in intel_timeline_init() local
[all …]
|
| H A D | intel_ring.h | 109 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
110 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) && in assert_ring_tail_valid()
112 #undef cacheline in assert_ring_tail_valid()
|
| H A D | selftest_timeline.c | 74 unsigned long cacheline; in __mock_hwsp_timeline() local
81 cacheline = hwsp_cacheline(tl); in __mock_hwsp_timeline()
82 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
86 cacheline); in __mock_hwsp_timeline()
|
| /netbsd-src/sys/arch/sparc64/dev/ |
| H A D | pci_machdep.c | 256 int bus_frequency, lt, cl, cacheline; in sparc64_pci_enumerate_bus1() local
274 cacheline = uimax(ecache_min_line_size, 64); in sparc64_pci_enumerate_bus1()
275 KASSERT((cacheline/64)*64 == cacheline && in sparc64_pci_enumerate_bus1()
276 (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline && in sparc64_pci_enumerate_bus1()
277 (cacheline/4)*4 == cacheline); in sparc64_pci_enumerate_bus1()
359 cl = cacheline; in sparc64_pci_enumerate_bus1()
|
| /netbsd-src/sys/dev/pci/ |
| H A D | if_ti.c | 1250 uint32_t cacheline; in ti_chipinit() local
1309 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); in ti_chipinit()
1319 switch (cacheline) { in ti_chipinit()
1332 device_xname(sc->sc_dev), cacheline); in ti_chipinit()
|
| H A D | pcireg.h | 445 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ argument
450 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | README.txt | 351 Make sure the instruction which starts a loop does not cross a cacheline
355 In the new trace, the hot loop has an instruction which crosses a cacheline
358 to grab the bytes from the next cacheline.
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/ |
| H A D | sync.md | 136 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
|
| H A D | i386.opt | 259 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
|
| /netbsd-src/sys/dev/microcode/aic7xxx/ |
| H A D | aic7xxx.seq | 753 * We fetch a "cacheline aligned" and sized amount of data
757 * cacheline size is unknown.
798 * If the ending address is on a cacheline boundary,
|
| H A D | aic79xx.seq | 1276 * We fetch a "cacheline aligned" and sized amount of data
1280 * cacheline size is unknown.
|
| H A D | aic7xxx.reg | 1305 * Partial transfer past cacheline end to be
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/ |
| H A D | sync.md | 143 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
|
| H A D | i386.opt | 259 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
|
| /netbsd-src/usr.sbin/makemandb/ |
| H A D | nostem.txt | 336 cacheline
|
| /netbsd-src/external/gpl3/gcc.old/dist/ |
| H A D | NEWS | 5895 the psABI, and -malign-data=cacheline uses increased alignment to
|
| /netbsd-src/external/gpl3/gcc/dist/ |
| H A D | NEWS | 7769 the psABI, and -malign-data=cacheline uses increased alignment to
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/doc/ |
| H A D | invoke.texi | 29250 psABI, and @samp{cacheline} uses increased alignment value to match
|
| H A D | gcc.info | 26729 'cacheline' uses increased alignment value to match the cache line
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/doc/ |
| H A D | invoke.texi | 32027 psABI, and @samp{cacheline} uses increased alignment value to match
|
| H A D | gcc.info | 29255 'cacheline' uses increased alignment value to match the cache line
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2014 | 741 for -malign-data=cacheline and the older GCC compatible
|