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Searched refs:c5 (Results 1 – 25 of 199) sorted by relevance

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/netbsd-src/external/mit/isl/dist/test_inputs/codegen/
H A Dshift2.c8 for (int c5 = max(0, -c2 + 1); c5 <= min(31, (c3 / 2) - c2 - 1); c5 += 1) variable
10 S_0(c0, c2 + c5, c3 + c6 - 1);
11 …for (int c5 = max(max(0, -c2 + 1), (c3 / 2) - c2); c5 <= min(min(31, length - c2 - 1), (c3 / 2) - … variable
12 for (int c6 = max(0, -c3 + 1); c6 <= min(length - c3, 2 * c2 - c3 + 2 * c5 - 1); c6 += 1)
13 S_0(c0, c2 + c5, c3 + c6 - 1);
14 S_3(c0, 0, c2 + c5);
15 if (length >= 2 * c2 + 2 * c5)
16 S_0(c0, c2 + c5, 2 * c2 + 2 * c5 - 1);
17 for (int c6 = 2 * c2 - c3 + 2 * c5 + 1; c6 <= min(31, length - c3); c6 += 1)
18 S_0(c0, c2 + c5, c3 + c6 - 1);
[all …]
H A Dcorrelation.c6 for (int c5 = 0; c5 <= min(31, m - c2 - 1); c5 += 1) variable
7 S_14(c2 + c5);
10 for (int c5 = max(0, c0 - c2 + c3); c5 <= min(31, 2 * c0 - c2 + 2 * c3 - 1); c5 += 1) variable
11 S_29(-c0 + c2 - c3 + c5, c0 + c3);
14 for (int c5 = 0; c5 <= min(31, 2 * c0 - c2 + 2 * c3 - 1); c5 += 1) variable
15 S_29(-c0 + c2 - c3 + c5, c0 + c3);
18 for (int c5 = max(0, c0 - c2 + c3); c5 <= min(31, 2 * c0 - c2 + 2 * c3 - 1); c5 += 1) variable
19 S_29(-c0 + c2 - c3 + c5, c0 + c3);
28 for (int c5 = max(0, c0 - c2 + c3 + 1); c5 <= min(31, m - c2 - 1); c5 += 1) { variable
30 S_14(c2 + c5);
[all …]
H A Dseparation_class4.c5 for (int c5 = c3 + 58; c5 <= -c3 + 61; c5 += 1) variable
6 S_0(c3, c5);
10 …for (int c5 = max(4 * c0 - c3 + 57, -4 * c0 + c3 + 58); c5 <= min(4 * c0 - c3 + 61, -4 * c0 + c3 +… variable
11 S_0(c3, c5);
15 …for (int c5 = max(-4 * c0 + c3 + 59, 4 * c0 - c3 + 62); c5 <= min(-4 * c0 + c3 + 63, 4 * c0 - c3 +… variable
16 S_0(c3, c5);
19 for (int c5 = -c3 + 569; c5 < c3 - 449; c5 += 1) variable
20 S_0(c3, c5);
H A Dlu.c7 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1) variable
8 S_6(c3, c4, c5);
11 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1) variable
12 S_2(c3, c5);
14 for (int c5 = max(c2, c3 + 1); c5 <= min(n - 1, c2 + 31); c5 += 1) variable
15 S_6(c3, c4, c5);
H A Dseparate2.c2 for (int c5 = 0; c5 <= 31; c5 += 1) variable
3 for (int c6 = max(0, 2 * (length % 16) + 2 * c5 - 62); c6 <= 30; c6 += 1) {
4 …) + 2 * c5 && 2 * (length % 16) >= c6 + 2 && 2 * (length % 16) + 2 * c5 >= c6 && 2 * (length % 32)…
6 if (length <= 15 && length >= c5 + 1 && c6 >= 1 && length >= c6)
7 S_0(c0, c5, c6 - 1);
H A Droman.c10 for (int c5 = 0; c5 < c3; c5 += 1) { variable
11 S_16(c1, c3, c5);
12 S_17(c1, c3, c5);
21 for (int c5 = 0; c5 < i + c1 - 2; c5 += 1) { variable
22 S_16(c1, i + c1 - 2, c5);
23 S_17(c1, i + c1 - 2, c5);
H A Dstride6.c3 …for (int c5 = max(max(0, -c1 - 1023), niter - c1 - c2 - 32); c5 <= min(min(31, -c1), niter - c1 - … variable
4 S_4(niter - 1, -c1 - c5);
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dmep-c5.cpu22 ; Insns introduced for the MeP-c5 core
29 (dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
32 (dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
35 (dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
44 (dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
53 (dnci pref "cache prefetch" ((MACH c5) VOLATILE)
62 (dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
71 (dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
82 (dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
93 (dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dmep-c5.cpu22 ; Insns introduced for the MeP-c5 core
29 (dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
32 (dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
35 (dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
44 (dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
53 (dnci pref "cache prefetch" ((MACH c5) VOLATILE)
62 (dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
71 (dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
82 (dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
93 (dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dmep-c5.cpu22 ; Insns introduced for the MeP-c5 core
29 (dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
32 (dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
35 (dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
44 (dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
53 (dnci pref "cache prefetch" ((MACH c5) VOLATILE)
62 (dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
71 (dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
82 (dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
93 (dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
[all …]
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dmep-c5.cpu22 ; Insns introduced for the MeP-c5 core
29 (dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)
32 (dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)
35 (dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
44 (dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
53 (dnci pref "cache prefetch" ((MACH c5) VOLATILE)
62 (dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
71 (dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
82 (dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
93 (dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
[all …]
/netbsd-src/external/mit/isl/dist/test_inputs/codegen/omega/
H A Dts1d-mp-i_ts-m_b-0.c14 …r (int c5 = max(0, -N - 500 * c1 + c4 + 2); c5 <= min(min(T - 500 * c1 - 1, -500 * c1 + c4 - 1), -… variable
15 s1(2, 500 * c1 + c5, 1, -500 * c1 + c4 - c5, 1);
21 …for (int c5 = max(0, -N - 500 * c1 + c4 + 2); c5 <= min(min(499, T - 500 * c1 - 1), -500 * c1 + c4… variable
22 s3(2, 500 * c1 + c5, 1, -500 * c1 + c4 - c5, 1);
28 …for (int c5 = max(-N - 500 * c1 + c4 + 2, -500 * c1 - 2000 * c3 + (c4 + 1) / 2); c5 <= min(min(499… variable
29 s5(2, 500 * c1 + c5, 1, -500 * c1 + c4 - c5, 1);
H A Dlefur04-0.c5 …c5 = max(max(max(max(0, 2 * c3 - 4), c1 - (-c1 + 3) / 3), c2 - (c2 + 3) / 3), c3 - (c3 + 3) / 3); … variable
6 …c5 - 501), 667 * c0 - 333 * c1 - (c0 + c1 + 3) / 3 - 332), 333 * c1 + c1 / 3), 333 * c2 + (c2 + 1)…
7 …ax(max(max(max(500 * c5 + 2, c6), 1000 * c0 - c6), 1000 * c3 - 2 * c6 + 2), 500 * c1 + (c6 + 1) / …
8 s0(c0, c1, c2, c3, c2 / 3, c5, c6, c7);
H A Dlefur03-0.c6 …c5 = max(max(max(c4, 1000 * c0 - c4), 1000 * c3 - 2 * c4 + 2), 500 * c1 + (c4 + 1) / 2); c5 <= min… variable
7 s0(c0, c1, c2, c3, c4, c5);
/netbsd-src/sys/arch/arm/arm/
H A Dcpufunc_asm_arm11x6.S70 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
135 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
153 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
156 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
185 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
188 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
H A Dcpufunc_asm_sa1.S67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
78 mcrne p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
96 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
100 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
114 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
198 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
217 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
268 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
304 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
H A Dcpufunc_asm_xscale.S122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
150 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
167 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
188 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
192 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
206 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
216 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
323 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
372 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
422 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
[all …]
H A Dcpufunc_asm_arm10.S43 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
47 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
53 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
56 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
H A Dcpufunc_asm_armv6.S52 mcrne p15, 0, r0, c7, c5, 0 /* Flush I cache */
71 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
84 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
126 mcrr p15, 0, r1, r0, c5 /* invalidate I cache range */
139 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
H A Dcpufunc_asm_arm9.S64 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
92 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
107 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
194 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
209 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
H A Dcpufunc_asm_armv5_ec.S64 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
90 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
105 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
187 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
202 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
H A Dcpufunc_asm_arm67.S59 mcrne p15, 0, r0, c5, c0, 0
74 mcr p15, 0, r0, c5, c0, 0
102 mcr p15, 0, r0, c5, c0, 0
/netbsd-src/crypto/external/bsd/openssl/dist/test/recipes/30-test_evp_pkey_provided/
H A DDH.priv.txt3 00:88:85:e7:9f:ee:6d:c5:7c:78:af:63:5d:38:2a:
10 fa:48:95:2e:38:d9:c5:e6:da:fb:6c:03:9d:4b:69:
12 79:24:ed:e1:d1:4a:57:f1:40:86:70:42:25:c5:27:
18 14:32:f9:ed:c2:12:d6:c5:c6:b3:e5:f2:6e:f6:16:
/netbsd-src/crypto/external/bsd/heimdal/dist/lib/hx509/data/
H A Dtest.crt19 b9:c5:56:89:ea:c2:d7:b1:96:69:fd:f7:4e:35:56:
23 b3:be:fb:e4:91:79:5e:c5:ba:f9:df:03:de:14:e2:
26 69:c0:36:da:e1:bc:24:fa:bd:8f:c5:ce:ca:d4:af:
27 b3:f1:d7:20:c1:ac:4d:31:42:c5:cd:6e:6c:41:0c:
39 09:59:10:6b:c5:f9:e7:4a:3f:76:eb:a2:63:8f:45:
41 c5:e5:65:1a:c7:d2:87:42:53:d3:a9:3f:fb:99:a0:
84 31:d7:06:fb:e7:ec:38:4f:3d:61:73:bf:b8:21:b0:c5:f8:3f:
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/whrlpool/
H A Dwp_block.c175 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7 argument
186 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
187 c7,c0,c1,c2,c3,c4,c5,c6, \
188 c6,c7,c0,c1,c2,c3,c4,c5, \
189 c5,c6,c7,c0,c1,c2,c3,c4, \
190 c4,c5,c6,c7,c0,c1,c2,c3, \
191 c3,c4,c5,c6,c7,c0,c1,c2, \
192 c2,c3,c4,c5,c6,c7,c0,c1, \
193 c1,c2,c3,c4,c5,c6,c7,c0
205 # define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ argument
[all …]

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