Searched refs:buildUndef (Results 1 – 11 of 11) sorted by relevance
573 buildUndef(ResIn); in buildSequence()584 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder664 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
223 MIRBuilder.buildUndef(CurResultReg); in insertParts()295 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()340 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()804 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()815 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()1308 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()1318 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()1431 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()1476 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); in widenWithUnmerge()3293 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); in fewerElementsVectorImplicitDef()[all …]
282 Register Undef = B.buildUndef(PartLLT).getReg(0); in mergeVectorRegsToResultRegs()494 Register Undef = B.buildUndef(SrcTy).getReg(0); in buildCopyToRegs()
202 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()235 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()316 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()2767 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()2841 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2102 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()2535 MIRBuilder.buildUndef(Undef); in translateLandingPad()2896 EntryBuilder->buildUndef(Reg); in translate()
2130 B.buildUndef(Dst); in legalizeExtractVectorElt()2163 B.buildUndef(Dst); in legalizeInsertVectorElt()2303 B.buildUndef(DstReg); in legalizeGlobalValue()3605 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()3614 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()3625 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()4049 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()4083 auto Undef = B.buildUndef(S32); in convertImageAddrToPacked()4150 B.buildUndef(MI.getOperand(0)); in legalizeImageIntrinsic()4450 Register Undef = B.buildUndef(Ty).getReg(0); in legalizeImageIntrinsic()
645 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
744 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop()1194 auto Undef = B.buildUndef(LoadTy); in applyMappingLoad()1894 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
408 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()420 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
711 auto Undef = B.buildUndef(SrcTy); in applyDupLane()
902 MachineInstrBuilder buildUndef(const DstOp &Res);