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Searched refs:buildCopy (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp146 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1))); in assignValueToReg()
147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0))); in assignValueToReg()
152 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
159 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
164 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
248 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0)); in assignValueToReg()
249 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1)); in assignValueToReg()
251 MIRBuilder.buildCopy(PhysReg, ValVReg); in assignValueToReg()
254 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
266 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
385 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
H A DX86CallLowering.cpp97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp78 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
112 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
201 SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0); in getStackAddress()
214 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
389 B.buildCopy(ReturnAddrVReg, LiveInReturn); in lowerReturn()
467 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
598 B.buildCopy(LiveInReturn, ReturnAddrReg); in lowerFormalArguments()
1091 MIRBuilder.buildCopy(LLT::vector(4, 32), FuncInfo.getScratchRSrcReg()); in handleImplicitCallArguments()
1092 MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg); in handleImplicitCallArguments()
1097 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
H A DAMDGPURegisterBankInfo.cpp845 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1093 Reg = B.buildCopy(Ty, Reg).getReg(0); in constrainOpWithReadfirstlane()
1278 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1406 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0); in setBufferOffsets()
1885 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
1934 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldExtractEltToCmpSelect()
1970 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
2019 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldInsertEltToCmpSelect()
2100 auto Copy = B.buildCopy(LLT::scalar(1), SrcReg); in applyMappingImpl()
2389 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
[all …]
H A DAMDGPULegalizerInfo.cpp2745 B.buildCopy(DstReg, LiveIn); in loadInputValue()
4570 B.buildCopy(SGPR01, LiveIn); in legalizeTrapHsaQueuePtr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
295 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
302 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp253 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
276 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
458 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
504 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
1009 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1147 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
H A DAArch64InstructionSelector.cpp919 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
1878 auto Copy = MIB.buildCopy(LLT::scalar(64), SrcOp); in preISelLower()
1905 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
2423 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2433 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3332 MIB.buildCopy(Register(AArch64::X0), LoadGOT.getReg(0)); in selectTLSGlobalValue()
3341 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0)); in selectTLSGlobalValue()
3622 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
4788 auto Copy = MIRBuilder.buildCopy(Dst, CPLoad->getOperand(0)); in emitConstantVector()
4971 MIB.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
[all …]
H A DAArch64PostLegalizerCombiner.cpp229 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp269 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
630 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
634 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
H A DIRTranslator.cpp328 MIRBuilder.buildCopy( in translateCompare()
331 MIRBuilder.buildCopy( in translateCompare()
1281 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1325 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1436 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1544 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2069 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2083 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2113 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2237 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
[all …]
H A DCSEMIRBuilder.cpp147 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
H A DCallLowering.cpp705 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr); in handleAssignments()
1144 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
1148 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg); in assignValueToReg()
H A DMachineIRBuilder.cpp238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy() function in MachineIRBuilder
503 return buildCopy(Dst, Src); in buildCast()
H A DLegalizerHelper.cpp871 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); in narrowScalar()
4940 MIRBuilder.buildCopy(DstReg, DstRegs[0]); in narrowScalarExtract()
6307 MIRBuilder.buildCopy(DstReg, Val); in lowerShuffleVector()
6356 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
6371 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
6372 MIRBuilder.buildCopy(Dst, SPTmp); in lowerDynStackAlloc()
6773 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
6775 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
H A DCombinerHelper.cpp128 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
334 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
685 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2293 Builder.buildCopy(DstReg, Reg); in applyCombineI2PToP2I()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DSplitKit.h451 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
H A DSplitKit.cpp548 SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg, in buildCopy() function in SplitEditor
632 Def = buildCopy(Edit->getReg(), Reg, LaneMask, MBB, I, Late, RegIdx); in defFromParent()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h505 Builder.buildCopy(DstReg, SrcReg); in replaceRegOrBuildCopy()
H A DMachineIRBuilder.h817 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);