| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 293 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces() 301 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); in buildLCMMergePieces() 342 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces() 834 auto K = MIRBuilder.buildConstant(NarrowTy, in narrowScalar() 844 auto K = MIRBuilder.buildConstant( in narrowScalar() 1088 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); in narrowScalar() 1151 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) in narrowScalar() 1373 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); in widenScalarMergeValues() 1536 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); in widenScalarUnmergeValues() 1667 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract() [all …]
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| H A D | CSEMIRBuilder.cpp | 192 return buildConstant(DstOps[0], *Cst); in buildInstr() 203 return buildConstant(Dst, *MaybeCst); in buildInstr() 234 MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in CSEMIRBuilder 238 return MachineIRBuilder::buildConstant(Res, Val); in buildConstant() 243 return buildSplatVector(Res, buildConstant(Ty.getElementType(), Val)); in buildConstant() 257 MachineInstrBuilder NewMIB = MachineIRBuilder::buildConstant(Res, Val); in buildConstant()
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| H A D | CombinerHelper.cpp | 1088 auto True = Builder.buildConstant( in applyOptBrCondByInvertingCond() 1195 return MIB.buildConstant(Ty, SplatVal).getReg(0); in getMemsetValue() 1202 return MIB.buildConstant(Ty, 0).getReg(0); in getMemsetValue() 1209 auto MagicMI = MIB.buildConstant(ExtType, Magic); in getMemsetValue() 1320 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), DstOff); in optimizeMemset() 1421 Offset = MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset) in optimizeMemcpy() 1517 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset); in optimizeMemmove() 1534 MIB.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), CurrOffset); in optimizeMemmove() 1694 auto NewOffset = MIB.buildConstant(OffsetTy, MatchInfo.Imm); in applyPtrAddImmedChain() 1763 Builder.buildConstant(MI.getOperand(0), 0); in applyShiftImmedChain() [all …]
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| H A D | MachineIRBuilder.cpp | 204 auto Cst = buildConstant(ValueTy, Value); in materializePtrAdd() 214 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits() 255 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder 276 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder 281 return buildConstant(Res, *CI); in buildConstant() 310 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant() function in MachineIRBuilder 313 return buildConstant(Res, *CI); in buildConstant() 383 auto ConstOffset = buildConstant(OffsetTy, Offset); in buildLoadFromOffset() 493 auto Mask = buildConstant( in buildZExtInReg() 665 auto Zero = buildConstant(LLT::scalar(64), 0); in buildShuffleSplat()
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| H A D | IRTranslator.cpp | 772 auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First); in emitJumpTableHeader() 860 auto Diff = MIB.buildConstant(CmpTy, High - Low); in emitSwitchCase() 1000 Register MinValReg = MIB.buildConstant(SwitchOpTy, B.First).getReg(0); in emitBitTestHeader() 1030 auto RangeCst = MIB.buildConstant(SwitchOpTy, B.Range); in emitBitTestHeader() 1056 MIB.buildConstant(SwitchTy, countTrailingZeros(B.Mask)); in emitBitTestCase() 1063 MIB.buildConstant(SwitchTy, countTrailingOnes(B.Mask)); in emitBitTestCase() 1068 auto CstOne = MIB.buildConstant(SwitchTy, 1); in emitBitTestCase() 1072 auto CstMask = MIB.buildConstant(SwitchTy, B.Mask); in emitBitTestCase() 1074 auto CstZero = MIB.buildConstant(SwitchTy, 0); in emitBitTestCase() 1505 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset); in translateGetElementPtr() [all …]
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| H A D | CallLowering.cpp | 1048 auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize); in copyArgumentMemory()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 103 auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0)); in applyExtractVecEltPairwiseAdd() 104 auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1)); in applyExtractVecEltPairwiseAdd() 211 auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt); in matchAArch64MulConstCombine() 221 B.buildSub(DstReg, B.buildConstant(Ty, 0), Res); in matchAArch64MulConstCombine() 226 B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes)); in matchAArch64MulConstCombine() 264 auto Cst1 = B.buildConstant(Ty, ShiftImm); in matchBitfieldExtractFromSExtInReg() 265 auto Cst2 = B.buildConstant(Ty, Width); in matchBitfieldExtractFromSExtInReg()
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| H A D | AArch64PreLegalizerCombiner.cpp | 57 MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt()); in applyFConstantToConstant() 103 auto WideZero = Builder.buildConstant(WideTy, 0); in applyICmpRedundantTrunc() 219 B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset))); in applyFoldGlobalOffset()
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| H A D | AArch64PostLegalizerLowering.cpp | 411 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT() 465 auto SrcCst = Builder.buildConstant(LLT::scalar(64), SrcLane); in applyINS() 467 auto DstCst = Builder.buildConstant(LLT::scalar(64), DstLane); in applyINS() 506 auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm); in applyVAshrLshrImm() 635 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred() 703 auto Lane = B.buildConstant(LLT::scalar(64), MatchInfo.second); in applyDupLane()
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| H A D | AArch64LegalizerInfo.cpp | 925 auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount); in legalizeShlAshrLshr() 991 MIRBuilder.buildConstant(IntPtrTy, Alignment.value() - 1); in legalizeVaArg() 1003 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrAlign)); in legalizeVaArg()
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| H A D | AArch64CallLowering.cpp | 255 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.h | 98 using MachineIRBuilder::buildConstant; 100 MachineInstrBuilder buildConstant(const DstOp &Res,
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| H A D | LegalizationArtifactCombiner.h | 89 Builder.buildConstant( in tryCombineAnyExt() 122 auto Mask = Builder.buildConstant( in tryCombineZExt() 149 Builder.buildConstant( in tryCombineZExt() 204 Builder.buildConstant( in tryCombineSExt() 231 Builder.buildConstant( in tryCombineTrunc() 343 Builder.buildConstant(DstReg, 0); in tryFoldImplicitDef()
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| H A D | MachineIRBuilder.h | 781 virtual MachineInstrBuilder buildConstant(const DstOp &Res, 792 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val); 793 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val); 1544 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1); in buildNot()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1762 auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1); in getSegmentAperture() 1830 auto HighAddr = B.buildConstant( in legalizeAddrSpaceCast() 1842 auto SegmentNull = B.buildConstant(DstTy, NullVal); in legalizeAddrSpaceCast() 1843 auto FlatNull = B.buildConstant(SrcTy, 0); in legalizeAddrSpaceCast() 1863 B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS)); in legalizeAddrSpaceCast() 1865 B.buildConstant(DstTy, TM.getNullPointerValue(DestAS)); in legalizeAddrSpaceCast() 1963 auto Const0 = B.buildConstant(S32, FractBits - 32); in extractF64Exponent() 1964 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent() 1971 return B.buildSub(S32, ExpPart, B.buildConstant(S32, 1023)); in extractF64Exponent() 1995 const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31); in legalizeIntrinsicTrunc() [all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 134 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank() 135 auto False = B.buildConstant(S32, 0); in applyBank() 1275 auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); in applyMappingDynStackAlloc() 1342 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets() 1343 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets() 1363 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets() 1371 VOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets() 1410 SOffsetReg = B.buildConstant(S32, 0).getReg(0); in setBufferOffsets() 1472 Register VIndex = B.buildConstant(S32, 0).getReg(0); in applyMappingSBufferLoad() 1567 auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6)); in applyMappingBFEIntrinsic() [all …]
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| H A D | AMDGPUPreLegalizerCombiner.cpp | 140 auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); in applyClampI64ToI16() 141 auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); in applyClampI64ToI16()
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| H A D | AMDGPUCallLowering.cpp | 203 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() 408 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() 859 Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0); in passSpecialInputs() 868 Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0); in passSpecialInputs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 374 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom() 379 auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); in legalizeCustom() 403 auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); in legalizeCustom() 438 auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); in legalizeCustom()
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| H A D | MipsCallLowering.cpp | 269 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLegalizerInfo.cpp | 410 MIRBuilder.buildConstant(OriginalResult, in legalizeCustom() 447 auto Zero = MIRBuilder.buildConstant(LLT::scalar(32), 0); in legalizeCustom() 463 MIRBuilder.buildConstant(MI.getOperand(0), in legalizeCustom()
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| H A D | ARMCallLowering.cpp | 103 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress()
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