| /netbsd-src/sys/external/bsd/drm2/dist/drm/ |
| H A D | drm_dsc.c | 100 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> in drm_dsc_pps_payload_pack() 109 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); in drm_dsc_pps_payload_pack() 279 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters() 288 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters() 323 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; in drm_dsc_compute_rc_parameters() 379 vdsc_cfg->bits_per_pixel, 16) + in drm_dsc_compute_rc_parameters() 382 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); in drm_dsc_compute_rc_parameters() 383 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()
|
| H A D | drm_fb_helper.c | 1221 return var_1->bits_per_pixel == var_2->bits_per_pixel && in drm_fb_pixel_format_equal() 1323 if (var->bits_per_pixel > fb->format->cpp[0] * 8 || in drm_fb_helper_check_var() 1328 var->xres, var->yres, var->bits_per_pixel, in drm_fb_helper_check_var() 1351 var->bits_per_pixel = fb->format->cpp[0] * 8; in drm_fb_helper_check_var() 1692 info->var.bits_per_pixel = fb->format->cpp[0] * 8; in drm_fb_helper_fill_var()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_dsc.c | 185 config->dc_dsc_cfg.bits_per_pixel, in dsc_config_log() 186 config->dc_dsc_cfg.bits_per_pixel / 16, in dsc_config_log() 187 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); in dsc_config_log() 282 int bits_per_pixel = pps->bits_per_pixel; in dsc_log_pps() local 292 …DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel … in dsc_log_pps() 349 …ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); /… in dsc_prepare_config() 359 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { in dsc_prepare_config() 389 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; in dsc_prepare_config() 391 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; in dsc_prepare_config() 393 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; in dsc_prepare_config()
|
| H A D | amdgpu_dcn20_resource.c | 2055 …pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.… in dcn20_populate_dml_pipes_from_context()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
| H A D | vmwgfx_fb.c | 109 int depth = var->bits_per_pixel; in vmw_fb_check_var() 113 switch (var->bits_per_pixel) { in vmw_fb_check_var() 118 DRM_ERROR("Bad bpp %u.\n", var->bits_per_pixel); in vmw_fb_check_var() 155 var->xres * var->bits_per_pixel/8, in vmw_fb_check_var() 432 switch (var->bits_per_pixel) { in vmw_fb_compute_depth() 437 DRM_ERROR("Bad bpp %u.\n", var->bits_per_pixel); in vmw_fb_compute_depth() 520 mode_cmd.pitches[0] = ((var->bits_per_pixel + 7) / 8) * mode_cmd.width; in vmw_fb_kms_framebuffer() 522 drm_mode_legacy_fb_format(var->bits_per_pixel, depth); in vmw_fb_kms_framebuffer() 587 DIV_ROUND_UP(var->bits_per_pixel, 8), in vmw_fb_set_par() 731 info->var.bits_per_pixel = fb_bpp; in vmw_fb_init()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| H A D | amdgpu_rc_calc_dpi.c | 51 to->bits_per_pixel = from->bits_per_pixel; in copy_pps_fields() 114 float bpp = ((float) pps->bits_per_pixel / 16.0); in dscc_compute_dsc_parameters()
|
| H A D | amdgpu_dc_dsc.c | 47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_dsc_bandwidth_in_kbps_from_timing() 606 dsc_cfg->bits_per_pixel = target_bpp; in setup_dsc_config()
|
| /netbsd-src/sys/dev/pci/ |
| H A D | machfb.c | 123 int bits_per_pixel; member 697 sc->bits_per_pixel = 8; in mach64_attach() 703 (sc->stride * (sc->bits_per_pixel / 8)) - 1; in mach64_attach() 715 sc->bits_per_pixel); in mach64_attach() 828 ri->ri_depth = sc->bits_per_pixel; in mach64_init_screen() 907 if (sc->bits_per_pixel == 8) in mach64_get_max_ramdac() 1087 switch (sc->bits_per_pixel) { in mach64_calc_crtcregs() 1179 if (sc->bits_per_pixel == 24) in mach64_init_engine() 1236 switch (sc->bits_per_pixel) { in mach64_init_engine() 1264 offset = ((x + y * sc->stride) * (sc->bits_per_pixel >> 3)) >> 3; [all …]
|
| /netbsd-src/sys/dev/scsipi/ |
| H A D | scsi_scanner.h | 85 u_int8_t bits_per_pixel; member
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_vdsc.c | 406 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params() 544 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure() 941 vdsc_cfg->bits_per_pixel = val; in intel_dsc_get_config() 942 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; in intel_dsc_get_config()
|
| H A D | intel_dp.c | 516 u32 bits_per_pixel, max_bpp_small_joiner_ram; in intel_dp_dsc_get_output_bpp() local 525 bits_per_pixel = (link_clock * lane_count * 8) / in intel_dp_dsc_get_output_bpp() 527 DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel); in intel_dp_dsc_get_output_bpp() 538 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); in intel_dp_dsc_get_output_bpp() 541 if (bits_per_pixel < valid_dsc_bpp[0]) { in intel_dp_dsc_get_output_bpp() 543 bits_per_pixel, valid_dsc_bpp[0]); in intel_dp_dsc_get_output_bpp() 549 if (bits_per_pixel < valid_dsc_bpp[i + 1]) in intel_dp_dsc_get_output_bpp() 552 bits_per_pixel = valid_dsc_bpp[i]; in intel_dp_dsc_get_output_bpp() 558 return bits_per_pixel << 4; in intel_dp_dsc_get_output_bpp()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| H A D | nouveau_nv50_fbcon.c | 105 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); in nv50_fbcon_imageblit() 163 switch (info->var.bits_per_pixel) { in nv50_fbcon_accel_init()
|
| H A D | nouveau_nvc0_fbcon.c | 105 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); in nvc0_fbcon_imageblit() 168 switch (info->var.bits_per_pixel) { in nvc0_fbcon_accel_init()
|
| H A D | nouveau_nv04_fbcon.c | 148 switch (info->var.bits_per_pixel) { in nv04_fbcon_accel_init()
|
| /netbsd-src/sys/arch/xen/xen/ |
| H A D | genfb_xen.c | 85 _xen_genfb_btinfo.depth = d0_consi->u.vesa_lfb.bits_per_pixel; in xen_genfb_getbtinfo()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/vboxvideo/ |
| H A D | modesetting.c | 51 p->bits_per_pixel = bpp; in hgsmi_process_display_info()
|
| H A D | vboxvideo.h | 288 u16 bits_per_pixel; member
|
| /netbsd-src/sys/external/bsd/drm2/dist/include/drm/ |
| H A D | drm_dsc.h | 131 u16 bits_per_pixel; member
|
| /netbsd-src/sys/external/mit/xen-include-public/dist/xen/include/public/ |
| H A D | xen.h | 911 uint16_t bits_per_pixel; member
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 561 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16; in set_dsc_configs_from_fairness_vars() 580 return dsc_config.bits_per_pixel; in bpp_x16_from_pbn()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dc_hw_types.h | 707 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ member
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc_stream.c | 117 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
|
| H A D | amdgpu_dc_link.c | 3200 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); in dc_bandwidth_in_kbps_from_timing()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | amdgpu_dce110_mem_input_v.c | 536 enum bits_per_pixel { in get_dvmm_hw_setting() enum
|
| /netbsd-src/external/mit/xorg/lib/libxcb/files/ |
| H A D | xproto.h | 276 uint8_t bits_per_pixel; member
|