Home
last modified time | relevance | path

Searched refs:addReg (Results 1 – 25 of 269) sorted by relevance

1234567891011

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
156 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
161 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
189 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
196 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
[all …]
H A DAVRFrameLowering.cpp72 .addReg(AVR::R1R0, RegState::Kill) in emitPrologue()
79 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
82 .addReg(AVR::R0, RegState::Define) in emitPrologue()
83 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
84 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
105 .addReg(AVR::SP) in emitPrologue()
122 .addReg(AVR::R29R28, RegState::Kill) in emitPrologue()
130 .addReg(AVR::R29R28) in emitPrologue()
149 .addReg(AVR::R0, RegState::Kill); in restoreStatusRegister()
204 .addReg(AVR::R29R28, RegState::Kill) in emitEpilogue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
147 .addReg(Scratch) in expandAtomicCmpSwapSubword()
148 .addReg(Mask); in expandAtomicCmpSwapSubword()
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB); in expandAtomicCmpSwapSubword()
158 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
159 .addReg(Mask2); in expandAtomicCmpSwapSubword()
161 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
162 .addReg(ShiftNewVal); in expandAtomicCmpSwapSubword()
164 .addReg(Scratch, RegState::Kill) in expandAtomicCmpSwapSubword()
165 .addReg(Ptr) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsFastISel.cpp221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
332 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
369 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
372 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
381 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
404 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
422 .addReg(MFI->getGlobalBaseReg(*MF)) in materializeGV()
428 .addReg(DestReg) in materializeGV()
[all …]
H A DMipsBranchExpansion.cpp347 MIB.addReg(MO.getReg()); in replaceBranch()
396 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
466 .addReg(Mips::SP) in expandToLongBranch()
469 .addReg(Mips::RA) in expandToLongBranch()
470 .addReg(Mips::SP) in expandToLongBranch()
497 .addReg(Mips::AT) in expandToLongBranch()
512 .addReg(Mips::RA) in expandToLongBranch()
513 .addReg(Mips::AT); in expandToLongBranch()
515 .addReg(Mips::SP) in expandToLongBranch()
527 .addReg(Mips::SP) in expandToLongBranch()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp234 .addReg(AddrReg); in doAtomicBinOpExpansion()
240 .addReg(DestReg) in doAtomicBinOpExpansion()
241 .addReg(IncrReg); in doAtomicBinOpExpansion()
243 .addReg(ScratchReg) in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
249 .addReg(ScratchReg); in doAtomicBinOpExpansion()
251 .addReg(ScratchReg) in doAtomicBinOpExpansion()
252 .addReg(RISCV::X0) in doAtomicBinOpExpansion()
268 .addReg(OldValReg) in insertMaskedMerge()
269 .addReg(NewValReg); in insertMaskedMerge()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp185 .addReg(TIP.first) in runOnMachineFunction()
188 .addReg(0)); in runOnMachineFunction()
1025 .addReg(0)); in emitJumpTableInsts()
1330 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1334 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1346 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
1350 .addReg(MI->getOperand(3).getReg())); in emitInstruction()
1357 .addReg(ARM::LR) in emitInstruction()
1358 .addReg(ARM::PC) in emitInstruction()
1361 .addReg(0) in emitInstruction()
[all …]
H A DARMExpandPseudoInsts.cpp556 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
560 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
562 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
564 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
566 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
627 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
688 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
690 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
692 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
694 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
[all …]
H A DARMFrameLowering.cpp378 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
383 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
393 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
398 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
408 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
629 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
639 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
640 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
646 .addReg(ARM::SP, RegState::Kill) in emitPrologue()
647 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp797 MIB.addReg(MustSaveCRs[0], RegState::Kill); in emitPrologue()
802 MIB.addReg(CRfield, RegState::ImplicitKill); in emitPrologue()
811 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
813 .addReg(SPReg); in emitPrologue()
825 .addReg(FPReg) in emitPrologue()
827 .addReg(SPReg); in emitPrologue()
830 .addReg(PPC::R30) in emitPrologue()
832 .addReg(SPReg); in emitPrologue()
835 .addReg(BPReg) in emitPrologue()
837 .addReg(SPReg); in emitPrologue()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrBuilder.h127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
177 MIB.addReg(AM.Base.Reg); in addFullAddress()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
189 return MIB.addReg(0); in addFullAddress()
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
[all …]
H A DX86FrameLowering.cpp248 .addReg(StackPtr) in emitSPUpdate()
249 .addReg(Reg); in emitSPUpdate()
262 .addReg(Rax, RegState::Kill) in emitSPUpdate()
274 .addReg(Rax) in emitSPUpdate()
275 .addReg(StackPtr); in emitSPUpdate()
279 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
301 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
356 .addReg(StackPtr) in BuildStackAdjustment()
578 .addReg(StackPtr) in emitStackProbeInlineGenericBlock()
602 .addReg(StackPtr) in emitStackProbeInlineGenericBlock()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset); in expandMEMCPY()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
161 .addReg(VE::SX10); in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
168 .addReg(VE::SX15); in emitPrologueInsns()
170 .addReg(VE::SX11) in emitPrologueInsns()
173 .addReg(VE::SX16); in emitPrologueInsns()
177 .addReg(VE::SX11) in emitPrologueInsns()
180 .addReg(VE::SX17); in emitPrologueInsns()
[all …]
H A DVEInstrInfo.cpp342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
366 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
384 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
385 .addReg(SubTmp, getKillRegState(true)); in copyPhysReg()
389 .addReg(VE::VM0) in copyPhysReg()
390 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
476 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
483 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
490 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
455 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
456 .addReg(DupDest, Src2IsKill); in optimizeVectElement()
462 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
467 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
566 .addReg(StReg[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1]); in optimizeLdStInterleave()
569 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
H A DAArch64AsmPrinter.cpp388 .addReg(AArch64::X16) in EmitHwasanMemaccessSymbols()
389 .addReg(Reg) in EmitHwasanMemaccessSymbols()
395 .addReg(AArch64::W16) in EmitHwasanMemaccessSymbols()
396 .addReg(IsShort ? AArch64::X20 : AArch64::X9) in EmitHwasanMemaccessSymbols()
397 .addReg(AArch64::X16) in EmitHwasanMemaccessSymbols()
403 .addReg(AArch64::XZR) in EmitHwasanMemaccessSymbols()
404 .addReg(AArch64::X16) in EmitHwasanMemaccessSymbols()
405 .addReg(Reg) in EmitHwasanMemaccessSymbols()
418 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI); in EmitHwasanMemaccessSymbols()
423 .addReg(AArch64::X16) in EmitHwasanMemaccessSymbols()
[all …]
H A DAArch64ExpandPseudoInsts.cpp149 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
158 .addReg(DstReg, RegState::Define | in expandMOVImm()
169 .addReg(DstReg, in expandMOVImm()
173 .addReg(DstReg) in expandMOVImm()
218 .addReg(AddrReg); in expandCMP_SWAP()
220 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in expandCMP_SWAP()
221 .addReg(DesiredReg) in expandCMP_SWAP()
226 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandCMP_SWAP()
234 .addReg(NewReg) in expandCMP_SWAP()
235 .addReg(AddrReg); in expandCMP_SWAP()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp34 LiveRegs.addReg(CSRegs[i]); in findScratchNonCalleeSaveRegister()
132 LiveRegs.addReg(SpillReg); in buildPrologSpill()
172 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
181 .addReg(GitPtrLo); in buildGitPtr()
248 .addReg(FlatScrInit) in emitEntryFunctionFlatScratchInit()
256 .addReg(FlatScrInitHi) in emitEntryFunctionFlatScratchInit()
275 .addReg(FlatScrInitLo) in emitEntryFunctionFlatScratchInit()
276 .addReg(ScratchWaveOffsetReg); in emitEntryFunctionFlatScratchInit()
278 .addReg(FlatScrInitHi) in emitEntryFunctionFlatScratchInit()
281 addReg(FlatScrInitLo). in emitEntryFunctionFlatScratchInit()
[all …]
H A DAMDGPUInstructionSelector.cpp160 .addReg(SrcReg); in selectCOPY()
163 .addReg(MaskedReg); in selectCOPY()
244 .addReg(Reg, 0, ComposedSubIdx); in getSubOperand64()
380 .addReg(CarryReg, RegState::Kill) in selectG_ADD_SUB()
388 .addReg(DstLo) in selectG_ADD_SUB()
390 .addReg(DstHi) in selectG_ADD_SUB()
428 .addReg(I.getOperand(4).getReg()); in selectG_UADDO_USUBO_UADDE_USUBE()
438 .addReg(AMDGPU::SCC); in selectG_UADDO_USUBO_UADDE_USUBE()
497 .addReg(SrcReg, 0, SubReg); in selectG_EXTRACT()
526 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp71 .addReg(FrameReg) in InsertFPImmInst()
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
78 .addReg(FrameReg) in InsertFPImmInst()
84 .addReg(FrameReg) in InsertFPImmInst()
107 .addReg(FrameReg) in InsertFPConstInst()
108 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
114 .addReg(FrameReg) in InsertFPConstInst()
115 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
120 .addReg(FrameReg) in InsertFPConstInst()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp62 .addReg(Reg) in loadImmediate()
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
110 MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
114 .addReg(Reg) in setRegTo()
115 .addReg(ScratchImmReg) in setRegTo()
116 .addReg(ScratchImmReg)}; in setRegTo()
119 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp649 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
652 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
658 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
660 .addReg(P.first); in splitMemRef()
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
664 .addReg(P.second); in splitMemRef()
676 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
742 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
750 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
768 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg()); in splitExt()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp90 .addReg(Reg) in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
103 .addReg(Reg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
108 .addReg(Reg) in loadImmediate()
109 .addReg(Reg) in loadImmediate()
114 .addReg(Reg) in loadImmediate()
122 .addReg(Reg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()

1234567891011