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Searched refs:addOperand (Results 1 – 25 of 177) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp447 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
452 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
457 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
462 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
481 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
486 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
491 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
496 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
501 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
506 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp304 ITInst.addOperand(MCOperand::createImm(ITState.Cond)); in flushPendingInstructions()
305 ITInst.addOperand(MCOperand::createImm(ITState.Mask)); in flushPendingInstructions()
2456 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
2458 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
2460 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
2475 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2477 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2482 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); in addVPTPredNOperands()
2484 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2501 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
260 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
284 Inst.addOperand(Reg); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
286 Inst.addOperand(S16); in HexagonProcessInstruction()
293 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
300 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
307 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
314 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
321 Inst.addOperand(MCOperand::createExpr(C255)); in HexagonProcessInstruction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
217 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
218 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
230 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
244 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); in decodeCondBrTarget()
76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
197 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
205 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
213 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
222 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); in decodeVSRpEvenOperands()
245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); in decodeMemRIOperands()
257 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp87 SICInst.addOperand(RD); in emitSIC()
95 BSICInst.addOperand(R1); in emitBSIC()
96 BSICInst.addOperand(R2); in emitBSIC()
98 BSICInst.addOperand(czero); in emitBSIC()
99 BSICInst.addOperand(czero); in emitBSIC()
107 LEAInst.addOperand(RD); in emitLEAzzi()
109 LEAInst.addOperand(CZero); in emitLEAzzi()
110 LEAInst.addOperand(CZero); in emitLEAzzi()
111 LEAInst.addOperand(Imm); in emitLEAzzi()
119 LEASLInst.addOperand(RD); in emitLEASLzzi()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstBuilder.h32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
38 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
44 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm()
50 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm()
56 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
62 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
67 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
68 Inst.addOperand(Op); in addOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
256 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
132 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
148 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
160 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
166 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
173 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
180 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
85 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
96 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
118 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
129 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
160 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
171 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass()
191 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM2RegisterClass()
211 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM4RegisterClass()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
181 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
205 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
223 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
230 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp39 NopInst.addOperand(MCOperand::createImm(0)); in getNop()
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
41 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1139 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1153 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
1238 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
1248 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairnospRegisterClass()
1262 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRspRegisterClass()
1292 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
1327 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass()
1358 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp384 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
389 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
398 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
408 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
543 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
549 NewInst.addOperand(I); in canonicalizeImmediates()
620 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
653 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
1238 TmpInst.addOperand(Rdd); in makeCombineInst()
1239 TmpInst.addOperand(MO1); in makeCombineInst()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
183 TmpInst.addOperand(Op1); in emitRX()
202 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
203 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII()
213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
214 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
215 TmpInst.addOperand(Op2); in emitRRX()
231 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
232 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp336 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
365 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
386 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
407 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
428 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
449 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
460 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
489 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64x8ClassRegisterClass()
501 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
522 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1046 MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp)); in LowerSTATEPOINT()
1077 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1084 MI.addOperand(Dest); in LowerFAULTING_OP()
1104 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1105 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
1113 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1114 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
1118 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1119 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
1123 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h512 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
514 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
519 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
527 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
536 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands()
570 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
576 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
578 Inst.addOperand(MCOperand::createReg(getMemDefaultBaseReg())); in addMemOperands()
579 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands()
580 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp152 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
202 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
213 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
255 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp817 Inst.addOperand(MCOperand::createImm(Imm)); in addExpr()
819 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
825 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
857 Inst.addOperand(MCOperand::createImm(Imm)); in addFenceArgOperands()
862 Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); in addCSRSystemRegisterOperands()
867 Inst.addOperand(MCOperand::createImm(getVType())); in addVTypeIOperands()
883 Inst.addOperand(MCOperand::createImm(getRoundingMode())); in addFRMArgOperands()
2246 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
2253 .addOperand(DestReg) in emitAuipcInstPair()
2254 .addOperand(TmpReg) in emitAuipcInstPair()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp129 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
164 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); in DecodeMEMrs9()
183 Inst.addOperand(MCOperand::createImm(Offset)); in DecodeSymbolicOperandOff()
201 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand()
213 Inst.addOperand( in DecodeFromCyclicRange()
230 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction()
231 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
248 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction()
249 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
266 Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); in DecodeLdRLImmInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp133 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI32RegisterClass()
143 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegisterClass()
153 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeF32RegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeF128RegisterClass()
177 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeV64RegisterClass()
187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVMRegisterClass()
197 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVM512RegisterClass()
209 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeMISCRegisterClass()
322 MI.addOperand(MCOperand::createImm(0)); in DecodeASX()
331 MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); in DecodeASX()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp155 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
156 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
157 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
162 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
163 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
164 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
169 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
170 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
175 Res.addOperand(MCOperand::createReg(RISCV::X1)); in relaxInstruction()
176 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Disassembler/
H A DWebAssemblyDisassembler.cpp104 MI.addOperand(MCOperand::createImm(Val)); in parseLEBImmediate()
116 MI.addOperand( in parseImmediate()
119 MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val))); in parseImmediate()
228 MI.addOperand( in getInstruction()
231 MI.addOperand(MCOperand::createImm(Val & 0x7f)); in getInstruction()
240 MI.addOperand(MCOperand::createExpr(Expr)); in getInstruction()
259 MI.addOperand(MCOperand::createImm(Val & 0x7f)); in getInstruction()
261 MI.addOperand( in getInstruction()

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