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Searched refs:__SHIFTOUT (Results 1 – 25 of 357) sorted by relevance

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/netbsd-src/sys/dev/usb/
H A Dxhcireg.h58 #define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXSLOTS_MASK)
60 #define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT((x), XHCI_HCS1_MAXINTRS_MASK)
62 #define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXPORTS_MASK)
66 #define XHCI_HCS2_IST(x) __SHIFTOUT((x), XHCI_HCS2_IST_MASK)
68 #define XHCI_HCS2_ERSTMAX(x) __SHIFTOUT((x), XHCI_HCS2_ERSTMAX_MASK)
71 #define XHCI_HCS2_SPR(x) __SHIFTOUT((x), XHCI_HCS2_SPR_MASK)
74 (__SHIFTOUT((x), XHCI_HCS2_SPBUFHI_MASK) << 5) | \
75 (__SHIFTOUT((x), XHCI_HCS2_SPBUFLO_MASK))
79 #define XHCI_HCS3_U1_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U1_DEL_MASK)
81 #define XHCI_HCS3_U2_DEL(x) __SHIFTOUT((
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H A Dohcireg.h48 #define OHCI_REV_LO(rev) __SHIFTOUT((rev), OHCI_REV_LO_MASK)
49 #define OHCI_REV_HI(rev) __SHIFTOUT((rev), OHCI_REV_HI_MASK)
51 #define OHCI_REV_LEGACY(rev) __SHIFTOUT((rev), OHCI_REV_LEGACY_MASK)
66 #define OHCI_GET_HCFS(x) __SHIFTOUT((x), OHCI_HCFS_MASK)
102 #define OHCI_FM_GET_IVAL(x) __SHIFTOUT((x), OHCI_FM_IVAL_MASK)
104 #define OHCI_FM_GET_FSMPS(x) __SHIFTOUT((x), OHCI_FM_FSMPS_MASK)
113 #define OHCI_RHD_GET_NDP(x) __SHIFTOUT((x), OHCI_RHD_NDP_MASK)
120 #define OHCI_RHD_GET_POTPGT(x) __SHIFTOUT((x), OHCI_RHD_POTPGT_MASK)
159 #define OHCI_ED_GET_FA(x) __SHIFTOUT((x), OHCI_ED_ADDR_MASK)
162 #define OHCI_ED_GET_EN(x) __SHIFTOUT((
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H A Dehcireg.h92 #define EHCI_HCC_GET_IST_THRESHOLD(x) __SHIFTOUT((x), EHCI_HCC_IST_THRESHOLD_MASK)
213 #define EHCI_ITD_GET_STATUS(x) __SHIFTOUT((x), EHCI_ITD_STATUS_MASK)
220 #define EHCI_ITD_GET_LEN(x) __SHIFTOUT((x), EHCI_ITD_LEN_MASK)
223 #define EHCI_ITD_GET_IOC(x) __SHIFTOUT((x), EHCI_ITD_IOC)
226 #define EHCI_ITD_GET_PG(x) __SHIFTOUT((x), EHCI_ITD_PG_MASK)
229 #define EHCI_ITD_GET_OFFS(x) __SHIFTOUT((x), EHCI_ITD_OFFSET_MASK)
236 #define EHCI_ITD_GET_EP(x) __SHIFTOUT((x), EHCI_ITD_EP_MASK)
239 #define EHCI_ITD_GET_DADDR(x) __SHIFTOUT((x), EHCI_ITD_DADDR_MASK)
242 #define EHCI_ITD_GET_DIR(x) __SHIFTOUT((x), EHCI_ITD_DIR_MASK)
245 #define EHCI_ITD_GET_MAXPKT(x) __SHIFTOUT((
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H A Duhcireg.h105 #define UHCI_PORTSC_GET_LS(p) __SHIFTOUT((p), UHCI_PORTSC_LS_MASK)
151 ((__SHIFTOUT((s), UHCI_TD_ACTLEN_MASK) + 1) & __SHIFTOUT_MASK(UHCI_TD_ACTLEN_MASK))
165 #define UHCI_TD_GET_ERRCNT(s) __SHIFTOUT((s), UHCI_TD_ERRCNT_MASK)
174 #define UHCI_TD_GET_PID(s) __SHIFTOUT((s), UHCI_TD_PID_MASK)
177 #define UHCI_TD_GET_DEVADDR(s) __SHIFTOUT((s), UHCI_TD_DEVADDR_MASK)
180 #define UHCI_TD_GET_ENDPT(s) __SHIFTOUT((s), UHCI_TD_ENDPT_MASK)
183 #define UHCI_TD_GET_DT(s) __SHIFTOUT((s), UHCI_TD_DT_MASK)
188 (__SHIFTOUT((s), UHCI_TD_MAXLEN_MASK) + 1)
/netbsd-src/sys/arch/aarch64/aarch64/
H A Dcpu.c258 variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK); in identify_aarch64_model()
259 revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK); in identify_aarch64_model()
342 __SHIFTOUT(ctr, CTR_EL0_CWG_LINE) * 4, in cpu_identify1()
343 __SHIFTOUT(ctr, CTR_EL0_ERG_LINE) * 4); in cpu_identify1()
347 sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE),
348 sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_IMIN_LINE),
349 __SHIFTOUT(ctr, CTR_EL0_DIC),
350 __SHIFTOUT(ctr, CTR_EL0_IDC),
351 __SHIFTOUT(clidr, CLIDR_LOUU),
352 __SHIFTOUT(clid
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H A Dcpufunc.c79 switch (__SHIFTOUT(mmfr2, ID_AA64MMFR2_EL1_CCIDX)) { in extract_cacheunit()
82 1 << (__SHIFTOUT(ccsidr, CCSIDR_LINESIZE) + 4); in extract_cacheunit()
83 cunit->cache_ways = __SHIFTOUT(ccsidr, CCSIDR_ASSOC) + 1; in extract_cacheunit()
84 cunit->cache_sets = __SHIFTOUT(ccsidr, CCSIDR_NUMSET) + 1; in extract_cacheunit()
88 1 << (__SHIFTOUT(ccsidr, CCSIDR64_LINESIZE) + 4); in extract_cacheunit()
89 cunit->cache_ways = __SHIFTOUT(ccsidr, CCSIDR64_ASSOC) + 1; in extract_cacheunit()
90 cunit->cache_sets = __SHIFTOUT(ccsidr, CCSIDR64_NUMSET) + 1; in extract_cacheunit()
112 switch (__SHIFTOUT(ctr, CTR_EL0_L1IP_MASK)) { in aarch64_getcacheinfo()
189 if (arm_dcache_maxline < __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE)) { in aarch64_parsecacheinfo()
190 arm_dcache_maxline = __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE); in aarch64_parsecacheinfo()
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H A Dtrap.c201 const uint32_t eclass = __SHIFTOUT(esr, ESR_EC); /* exception class */ in trap_el1h_sync()
222 if (__SHIFTOUT(esr, ESR_ISS) == 0x40d && in trap_el1h_sync()
288 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DMIN_LINE) > in configure_cpu_traps0()
289 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DMIN_LINE)) || in configure_cpu_traps0()
290 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IMIN_LINE) > in configure_cpu_traps0()
291 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IMIN_LINE))) in configure_cpu_traps0()
294 if ((__SHIFTOUT(ctr_el0_raw, CTR_EL0_DIC) == 1 && in configure_cpu_traps0()
295 __SHIFTOUT(ctr_el0_usr, CTR_EL0_DIC) == 0) || in configure_cpu_traps0()
296 (__SHIFTOUT(ctr_el0_raw, CTR_EL0_IDC) == 1 && in configure_cpu_traps0()
297 __SHIFTOUT(ctr_el0_usr, CTR_EL0_IDC) == 0)) in configure_cpu_traps0()
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/netbsd-src/sys/arch/riscv/riscv/
H A Dkobj_machdep.c342 const uint32_t immA = __SHIFTOUT(addend, __BIT(12)); in kobj_reloc()
343 const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 5)); in kobj_reloc()
344 const uint32_t immC = __SHIFTOUT(addend, __BITS( 4, 1)); in kobj_reloc()
345 const uint32_t immD = __SHIFTOUT(addend, __BIT(11)); in kobj_reloc()
364 const uint32_t immA = __SHIFTOUT(addend, __BIT(20)); in kobj_reloc()
365 const uint32_t immB = __SHIFTOUT(addend, __BITS(10, 1)); in kobj_reloc()
366 const uint32_t immC = __SHIFTOUT(addend, __BIT(11)); in kobj_reloc()
367 const uint32_t immD = __SHIFTOUT(addend, __BITS(19, 12)); in kobj_reloc()
407 const uint32_t immA = __SHIFTOUT(addend, __BITS(11, 5)); in kobj_reloc()
408 const uint32_t immB = __SHIFTOUT(addend, __BITS( 4, 0)); in kobj_reloc()
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/netbsd-src/sys/arch/arm/imx/
H A Dimx51_ccm.c177 switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) { in imx51_get_clock()
184 (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF)); in imx51_get_clock()
187 (1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF)); in imx51_get_clock()
215 switch (__SHIFTOUT(cbcdr, CBCDR_PERIPH_CLK_SEL)) { in imx51_get_clock()
234 switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) { in imx51_get_clock()
255 return freq / (1 + __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF)); in imx51_get_clock()
261 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF)); in imx51_get_clock()
265 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF)); in imx51_get_clock()
286 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1); in imx51_get_clock()
287 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2); in imx51_get_clock()
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/
H A Ddriver-aarch64.cc409 unsigned cimp = __SHIFTOUT(id.ac_midr, MIDR_EL1_IMPL); in host_detect_local_cpu()
419 unsigned cvariant = __SHIFTOUT(id.ac_midr, MIDR_EL1_VARIANT); in host_detect_local_cpu()
428 unsigned ccore = __SHIFTOUT(id.ac_midr, MIDR_EL1_PARTNUM); in host_detect_local_cpu()
442 if (__SHIFTOUT(id.ac_aa64pfr0, ID_AA64PFR0_EL1_FP) == ID_AA64PFR0_EL1_FP_IMPL) in host_detect_local_cpu()
444 if (__SHIFTOUT(id.ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD) == ID_AA64PFR0_EL1_ADV_SIMD_IMPL) in host_detect_local_cpu()
447 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_RDM) == ID_AA64ISAR0_EL1_RDM_SQRDML) in host_detect_local_cpu()
449 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_DP) == ID_AA64ISAR0_EL1_DP_UDOT) in host_detect_local_cpu()
451 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_FHM) == ID_AA64ISAR0_EL1_FHM_FMLAL) in host_detect_local_cpu()
454 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_AES) == ID_AA64ISAR0_EL1_AES_AES) in host_detect_local_cpu()
456 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_AES) == ID_AA64ISAR0_EL1_AES_PMUL) in host_detect_local_cpu()
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Ddriver-aarch64.c409 unsigned cimp = __SHIFTOUT(id.ac_midr, MIDR_EL1_IMPL); in host_detect_local_cpu()
419 unsigned cvariant = __SHIFTOUT(id.ac_midr, MIDR_EL1_VARIANT); in host_detect_local_cpu()
428 unsigned ccore = __SHIFTOUT(id.ac_midr, MIDR_EL1_PARTNUM); in host_detect_local_cpu()
442 if (__SHIFTOUT(id.ac_aa64pfr0, ID_AA64PFR0_EL1_FP) == ID_AA64PFR0_EL1_FP_IMPL) in host_detect_local_cpu()
444 if (__SHIFTOUT(id.ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD) == ID_AA64PFR0_EL1_ADV_SIMD_IMPL) in host_detect_local_cpu()
447 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_RDM) == ID_AA64ISAR0_EL1_RDM_SQRDML) in host_detect_local_cpu()
449 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_DP) == ID_AA64ISAR0_EL1_DP_UDOT) in host_detect_local_cpu()
451 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_FHM) == ID_AA64ISAR0_EL1_FHM_FMLAL) in host_detect_local_cpu()
454 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_AES) == ID_AA64ISAR0_EL1_AES_AES) in host_detect_local_cpu()
456 if (__SHIFTOUT(id.ac_aa64isar0, ID_AA64ISAR0_EL1_AES) == ID_AA64ISAR0_EL1_AES_PMUL) in host_detect_local_cpu()
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/netbsd-src/sys/arch/arm/rockchip/
H A Drk_cru_pll.c115 const u_int nr = __SHIFTOUT(con0, RK3288_CLKR) + 1; in rk_cru_pll_get_rate()
116 const u_int no = __SHIFTOUT(con0, RK3288_CLKOD) + 1; in rk_cru_pll_get_rate()
117 const u_int nf = __SHIFTOUT(con1, RK3288_CLKF) + 1; in rk_cru_pll_get_rate()
123 const uint64_t m = __SHIFTOUT(con0, RK3588_PLLCON0_M); in rk_cru_pll_get_rate()
124 const uint64_t p = __SHIFTOUT(con1, RK3588_PLLCON1_P); in rk_cru_pll_get_rate()
125 const uint64_t s = __SHIFTOUT(con1, RK3588_PLLCON1_S); in rk_cru_pll_get_rate()
126 const uint64_t k = __SHIFTOUT(con2, RK3588_PLLCON2_K); in rk_cru_pll_get_rate()
136 const u_int postdiv1 = __SHIFTOUT(con0, PLL_POSTDIV1); in rk_cru_pll_get_rate()
137 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); in rk_cru_pll_get_rate()
138 const u_int dsmpd = __SHIFTOUT(con1, PLL_DSMPD); in rk_cru_pll_get_rate()
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/netbsd-src/sys/sys/
H A Dagpio.h46 #define AGP_MODE_GET_RQ(x) __SHIFTOUT((x), AGP_MODE_RQ)
47 #define AGP_MODE_GET_ARQSZ(x) __SHIFTOUT((x), AGP_MODE_ARQSZ)
48 #define AGP_MODE_GET_CAL(x) __SHIFTOUT((x), AGP_MODE_CAL)
49 #define AGP_MODE_GET_SBA(x) __SHIFTOUT((x), AGP_MODE_SBA)
50 #define AGP_MODE_GET_AGP(x) __SHIFTOUT((x), AGP_MODE_AGP)
51 #define AGP_MODE_GET_4G(x) __SHIFTOUT((x), AGP_MODE_4G)
52 #define AGP_MODE_GET_FW(x) __SHIFTOUT((x), AGP_MODE_FW)
53 #define AGP_MODE_GET_MODE_3(x) __SHIFTOUT((x), AGP_MODE_MODE_3)
54 #define AGP_MODE_GET_RATE(x) __SHIFTOUT((x), AGP_MODE_RATE)
/netbsd-src/sys/arch/arm/arm32/
H A Ddb_machdep.c271 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); in tlb_decode_cortex_a5_vpn()
272 return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1) in tlb_decode_cortex_a5_vpn()
285 const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA); in tlb_print_cortex_a5_entry()
290 const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE); in tlb_print_cortex_a5_entry()
291 const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM); in tlb_print_cortex_a5_entry()
292 const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP); in tlb_print_cortex_a5_entry()
298 const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID); in tlb_print_cortex_a5_entry()
302 const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX); in tlb_print_cortex_a5_entry()
332 const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE); in tlb_decode_cortex_a7_vpn()
337 return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1) in tlb_decode_cortex_a7_vpn()
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/netbsd-src/sys/external/bsd/drm2/linux/
H A Dlinux_hdmi.c203 frame->coding_type = __SHIFTOUT(p[0], __BITS(7,4)); in hdmi_audio_infoframe_unpack()
204 frame->channels = __SHIFTOUT(p[0], __BITS(2,0)); in hdmi_audio_infoframe_unpack()
206 frame->sample_frequency = __SHIFTOUT(p[1], __BITS(4,2)); in hdmi_audio_infoframe_unpack()
207 frame->sample_size = __SHIFTOUT(p[1], __BITS(1,0)); in hdmi_audio_infoframe_unpack()
209 frame->coding_type_ext = __SHIFTOUT(p[2], __BITS(5,0)); in hdmi_audio_infoframe_unpack()
211 frame->level_shift_value = __SHIFTOUT(p[3], __BITS(6,3)); in hdmi_audio_infoframe_unpack()
213 frame->downmix_inhibit = __SHIFTOUT(p[4], __BIT(7)); in hdmi_audio_infoframe_unpack()
311 frame->colorspace = __SHIFTOUT(p[0], __BITS(6,5)); in hdmi_avi_infoframe_unpack()
312 frame->scan_mode = __SHIFTOUT(p[0], __BITS(1,0)); in hdmi_avi_infoframe_unpack()
314 frame->colorimetry = __SHIFTOUT(p[1], __BITS(7,6)); in hdmi_avi_infoframe_unpack()
[all …]
/netbsd-src/sys/dev/vmt/
H A Dvmt_subr.c157 if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == 0xffffffff || in vmt_probe()
158 __SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_MAGIC) in vmt_probe()
162 if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == VM_MAGIC) in vmt_probe()
180 if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) == 0xffffffff || in vmt_common_attach()
181 __SHIFTOUT(frame.ebx, VM_REG_WORD_MASK) != VM_MAGIC) { in vmt_common_attach()
193 bswap32(__SHIFTOUT(frame.eax, VM_REG_WORD_MASK)); in vmt_common_attach()
194 u = bswap32(__SHIFTOUT(frame.ebx, VM_REG_WORD_MASK)); in vmt_common_attach()
197 u = bswap32(__SHIFTOUT(frame.ecx, VM_REG_WORD_MASK)); in vmt_common_attach()
202 u = bswap32(__SHIFTOUT(frame.edx, VM_REG_WORD_MASK)); in vmt_common_attach()
476 if (__SHIFTOUT(frame.eax, VM_REG_WORD_MASK) != 0xffffffff) { in vmt_sync_guest_clock()
[all …]
/netbsd-src/lib/libc/arch/arm/hardfloat/
H A Dfpgetround.c59 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RN, VFP_FPSCR_RMODE) == FP_RN); in __weak_alias()
60 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RP, VFP_FPSCR_RMODE) == FP_RP); in __weak_alias()
61 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RM, VFP_FPSCR_RMODE) == FP_RM); in __weak_alias()
62 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RZ, VFP_FPSCR_RMODE) == FP_RZ); in __weak_alias()
65 return __SHIFTOUT(fpscr, VFP_FPSCR_RMODE); in __weak_alias()
H A Dfpsetround.c59 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RN, VFP_FPSCR_RMODE) == FP_RN); in __weak_alias()
60 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RP, VFP_FPSCR_RMODE) == FP_RP); in __weak_alias()
61 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RM, VFP_FPSCR_RMODE) == FP_RM); in __weak_alias()
62 __CTASSERT(__SHIFTOUT(VFP_FPSCR_RZ, VFP_FPSCR_RMODE) == FP_RZ); in __weak_alias()
65 fp_rnd old_rnd = __SHIFTOUT(fpscr, VFP_FPSCR_RMODE); in __weak_alias()
/netbsd-src/sys/arch/arm/broadcom/
H A Dbcm53xx_board.c161 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) in bcm53xx_memprobe()
162 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); in bcm53xx_memprobe()
163 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) in bcm53xx_memprobe()
164 - __SHIFTOUT(v82, CTL_82_COL_DIFF); in bcm53xx_memprobe()
165 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); in bcm53xx_memprobe()
170 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); in bcm53xx_memprobe()
171 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); in bcm53xx_memprobe()
214 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; in bcm53xx_value_wrap()
225 const uint32_t ndiv_frac = __SHIFTOUT(control5, in bcm53xx_genpll_clock_init()
253 const uint32_t ndiv_frac = __SHIFTOUT(control1, in bcm53xx_lcpll_clock_init()
[all …]
/netbsd-src/lib/libm/arch/arm/
H A Dfenv.c94 *flagp = __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_CSUM) & excepts; in fegetexceptflag()
145 return __SHIFTOUT(fpscr, VFP_FPSCR_ESUM) & FE_ALL_EXCEPT; in feenableexcept()
156 return __SHIFTOUT(fpscr, VFP_FPSCR_ESUM) & FE_ALL_EXCEPT; in fedisableexcept()
168 return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_CSUM) & excepts; in fetestexcept()
174 return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_ESUM); in fegetexcept()
183 return __SHIFTOUT(armreg_fpscr_read(), VFP_FPSCR_RMODE); in fegetround()
195 _DIAGASSERT(!(round & ~__SHIFTOUT(VFP_FPSCR_RMODE, VFP_FPSCR_RMODE))); in fesetround()
/netbsd-src/sys/arch/x86/x86/
H A Dcpu_topology.c117 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); in x86_cpu_topology()
128 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) in x86_cpu_topology()
148 core_max = __SHIFTOUT(descs[2], CPUID_CAPEX_NC) + 1; in x86_cpu_topology()
150 n = __SHIFTOUT(descs[2], CPUID_CAPEX_ApicIdSize); in x86_cpu_topology()
191 const u_int threads = __SHIFTOUT(descs[1], in x86_cpu_topology()
208 core_id = __SHIFTOUT(apic_id, core_mask); in x86_cpu_topology()
212 smt_id = __SHIFTOUT(apic_id, smt_mask); in x86_cpu_topology()
/netbsd-src/lib/libm/arch/aarch64/
H A Dfenv.c94 *flagp = __SHIFTOUT(reg_fpsr_read(), FPSR_CSUM) & excepts; in fegetexceptflag()
147 return __SHIFTOUT(reg_fpsr_read(), FPSR_CSUM) & excepts; in fetestexcept()
156 return __SHIFTOUT(reg_fpcr_read(), FPCR_RMODE); in fegetround()
168 _DIAGASSERT(!(round & ~__SHIFTOUT(FPCR_RMODE, FPCR_RMODE))); in fesetround()
241 return __SHIFTOUT(__fpcr, FPCR_ESUM); in feenableexcept()
249 return __SHIFTOUT(__fpcr, FPCR_ESUM); in fedisableexcept()
256 return __SHIFTOUT(__fpcr, FPCR_ESUM); in fegetexcept()
/netbsd-src/sys/arch/arm/cortex/
H A Dpl310.c164 u_int rev = __SHIFTOUT(id, CACHE_ID_REV); in arml2cc_attach()
267 info->cache_type = __SHIFTOUT(cfg, CACHE_TYPE_CTYPE); in arml2cc_init()
268 info->cache_unified = __SHIFTOUT(cfg, CACHE_TYPE_HARVARD) == 0; in arml2cc_init()
269 u_int cfg_dsize = __SHIFTOUT(cfg, CACHE_TYPE_DSIZE); in arml2cc_init()
271 u_int d_waysize = 8192 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xWAYSIZE); in arml2cc_init()
272 info->dcache_ways = 8 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xASSOC); in arml2cc_init()
273 info->dcache_line_size = 32 << __SHIFTOUT(cfg_dsize, CACHE_TYPE_xLINESIZE); in arml2cc_init()
283 u_int cfg_isize = __SHIFTOUT(cfg, CACHE_TYPE_ISIZE); in arml2cc_init()
284 u_int i_waysize = 8192 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xWAYSIZE); in arml2cc_init()
285 info->icache_ways = 8 << __SHIFTOUT(cfg_isize, CACHE_TYPE_xASSOC); in arml2cc_init()
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/netbsd-src/sys/arch/evbppc/mpc85xx/
H A Dpixisreg.h38 #define PX_VER_ID_GET(n) __SHIFTOUT((n), PX_VER_ID)
40 #define PX_VER_REV_GET(n) __SHIFTOUT((n), PX_VER_ID)
45 #define PX_CSR_EVES_GET(n) __SHIFTOUT((n), PX_CSR_EVES)
63 #define PX_SPD_SYSCLK_GET(n) __SHIFTOUT((n), PX_SPD_SYSCLK)
73 #define PX_SPD_DDRCLK_GET(n) __SHIFTOUT((n), PX_SPD_DDRCLK)
/netbsd-src/sys/arch/arm/arm/
H A Darm_cpu_topology.c59 pkgid = __SHIFTOUT(mpidr, MPIDR_AFF2); in arm_cpu_topology_set()
60 coreid = __SHIFTOUT(mpidr, MPIDR_AFF1); in arm_cpu_topology_set()
61 smtid = __SHIFTOUT(mpidr, MPIDR_AFF0); in arm_cpu_topology_set()
63 pkgid = __SHIFTOUT(mpidr, MPIDR_AFF1); in arm_cpu_topology_set()
64 coreid = __SHIFTOUT(mpidr, MPIDR_AFF0); in arm_cpu_topology_set()

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