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Searched refs:ZeroReg (Results 1 – 24 of 24) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp74 unsigned ZeroReg; in loadImmediate() local
77 ZeroReg = Mips::ZERO; in loadImmediate()
82 ZeroReg = Mips::ZERO_64; in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp800 ZeroReg = InProlog ? X86::RCX in emitStackProbeInlineWindowsCoreCLR64() local
860 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
861 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
862 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
869 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
145 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3169 Register ZeroReg, RegisterOperand GPROpnd> {
3177 (Addiu ZeroReg, tglobaladdr:$in)>;
3179 (Addiu ZeroReg, tblockaddress:$in)>;
3181 (Addiu ZeroReg, tjumptable:$in)>;
3183 (Addiu ZeroReg, tconstpool:$in)>;
3185 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3187 (Addiu ZeroReg, texternalsym:$in)>;
/netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/internal/
H A Datomic.d131 enum ZeroReg = SizedReg!(DX, T); in version() local
142 }, [SrcReg, ZeroReg, ResReg])); in version()
150 enum ZeroReg = SizedReg!(DX, T); in version() local
162 }, [SrcReg, ZeroReg, ResReg])); in version()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1473 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1476 .addReg(ZeroReg).addImm(1) in SelectCmp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3205 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
3220 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4504 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4523 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4533 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4534 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4594 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
4596 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
5250 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5255 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64ExpandPseudoInsts.cpp76 unsigned ExtendImm, unsigned ZeroReg,
186 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64InstrInfo.h162 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64FastISel.cpp380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
383 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4845 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4848 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
H A DAArch64ISelDAGToDAG.cpp2805 unsigned ZeroReg; in tryShiftAmountMod() local
2809 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2813 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2816 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64ISelLowering.cpp14429 unsigned ZeroReg; in replaceZeroVectorStore() local
14432 ZeroReg = AArch64::WZR; in replaceZeroVectorStore()
14435 ZeroReg = AArch64::XZR; in replaceZeroVectorStore()
14439 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); in replaceZeroVectorStore()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2721 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2741 SrcReg = ZeroReg; in loadImmediate()
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2787 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2816 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
4189 unsigned ZeroReg; in expandDivRem() local
4194 ZeroReg = Mips::ZERO_64; in expandDivRem()
4198 ZeroReg = Mips::ZERO; in expandDivRem()
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4229 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h872 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
876 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
882 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2160 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
2162 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
2163 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
2164 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2091 MCRegister ZeroReg; in onlyFoldImmediate() local
2094 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2096 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2100 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp11191 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
11258 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
11303 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
11347 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12238 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
12271 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
12328 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12352 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12365 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp4252 const Register ZeroReg = AArch64::WZR; in emitCSetForFCmp() local
4255 MIRBuilder.buildInstr(AArch64::CSINCWr, {CsetDst}, {ZeroReg, ZeroReg}) in emitCSetForFCmp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7227 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
7229 ZeroReg, 0); in convertNonUniformLoopRegion()
7230 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()