Searched refs:XVT (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1039 shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument 1042 if (XVT.isVector()) in shouldTransformSignedTruncationCheck() 1053 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| H A D | X86ISelDAGToDAG.cpp | 3582 MVT XVT = X.getSimpleValueType(); in matchBitExtract() local 3618 if (XVT != MVT::i32) { in matchBitExtract() 3619 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract() 3624 SDValue Extract = CurDAG->getNode(X86ISD::BEXTR, DL, XVT, X, Control); in matchBitExtract() 3627 if (XVT != NVT) { in matchBitExtract()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 746 bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument 749 if (XVT.isVector()) in shouldTransformSignedTruncationCheck() 760 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3228 EVT XVT = X.getValueType(); in optimizeSetCCOfSignedTruncationCheck() local 3263 assert(XVT.isInteger()); in optimizeSetCCOfSignedTruncationCheck() 3264 NewCond = getSetCCInverse(NewCond, XVT); in optimizeSetCCOfSignedTruncationCheck() 3277 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck() 3282 XVT, KeptBits)) in optimizeSetCCOfSignedTruncationCheck() 3285 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; in optimizeSetCCOfSignedTruncationCheck() 3286 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck() 3290 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); in optimizeSetCCOfSignedTruncationCheck() 3291 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck() 3292 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
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| H A D | DAGCombiner.cpp | 4802 EVT XVT = X.getValueType(); in hoistLogicOpWithSameOpcodeHands() local 4811 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands() 4816 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands() 4821 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands() 4824 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands() 4835 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands() 4838 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands() 4842 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) in hoistLogicOpWithSameOpcodeHands() 4844 if (!TLI.isTypeLegal(XVT)) in hoistLogicOpWithSameOpcodeHands() 4846 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 725 virtual bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3087 EVT XVT = X.getValueType(); in performShlCombine() local 3088 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
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