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/netbsd-src/crypto/external/bsd/openssl/dist/crypto/aes/asm/
H A Dbsaes-armv7.pl71 my @XMM=map("q$_",(0..15));
596 veor @XMM[5], @t[5], @t[6]
597 veor @XMM[6], @t[6], @y[6] @ t[6]=y[6]
598 veor @XMM[2], @t[2], @t[6]
599 veor @XMM[7], @t[7], @y[7] @ t[7]=y[7]
601 vmov @XMM[0], @t[0]
602 vmov @XMM[1], @t[1]
603 @ vmov @XMM[2], @t[2]
604 vmov @XMM[3], @t[3]
605 vmov @XMM[4], @t[4]
[all …]
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/aes/asm/
H A Dbsaes-armv7.pl69 my @XMM=map("q$_",(0..15));
594 veor @XMM[5], @t[5], @t[6]
595 veor @XMM[6], @t[6], @y[6] @ t[6]=y[6]
596 veor @XMM[2], @t[2], @t[6]
597 veor @XMM[7], @t[7], @y[7] @ t[7]=y[7]
599 vmov @XMM[0], @t[0]
600 vmov @XMM[1], @t[1]
601 @ vmov @XMM[2], @t[2]
602 vmov @XMM[3], @t[3]
603 vmov @XMM[4], @t[4]
[all …]
/netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/
H A Dsimd.d98 enum XMM in version() enum
413 pure @safe void16 __simd(XMM opcode, void16 op1, void16 op2); in version()
419 a = cast(float4)__simd(XMM.PXOR, a, a); in version()
425 pure @safe void16 __simd(XMM opcode, void16 op1); in version()
426 pure @safe void16 __simd(XMM opcode, double d); /// in version()
427 pure @safe void16 __simd(XMM opcode, float f); /// in version()
433 a = cast(float4)__simd(XMM.LODSS, a); in version()
451 pure @safe void16 __simd(XMM opcode, void16 op1, void16 op2, ubyte imm8); in version()
457 a = cast(float4)__simd(XMM.CMPPD, a, a, 0x7A); in version()
471 pure @safe void16 __simd_ib(XMM opcode, void16 op1, ubyte imm8); in version()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrXOP.td16 [(set VR128:$dst, (Int VR128:$src))]>, XOP, Sched<[SchedWritePHAdd.XMM]>;
20 Sched<[SchedWritePHAdd.XMM.Folded, SchedWritePHAdd.XMM.ReadAfterFold]>;
80 SchedWriteFRnd.XMM>;
89 SchedWriteFRnd.XMM>;
126 defm VPROTB : xop3op<0x90, "vprotb", rotl, v16i8, SchedWriteVarVecShift.XMM>;
127 defm VPROTD : xop3op<0x92, "vprotd", rotl, v4i32, SchedWriteVarVecShift.XMM>;
128 defm VPROTQ : xop3op<0x93, "vprotq", rotl, v2i64, SchedWriteVarVecShift.XMM>;
129 defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>;
130 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8, SchedWriteVarVecShift.XMM>;
131 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32, SchedWriteVarVecShift.XMM>;
[all …]
H A DX86Schedule.td84 X86FoldableSchedWrite XMM = s128; // XMM operations.
118 X86SchedWriteMoveLS XMM = s128; // XMM operations.
238 defm WriteFAddX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point add/sub (XMM).
242 defm WriteFAdd64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double add/sub (XMM).
246 defm WriteFCmpX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point compare (XMM).
250 defm WriteFCmp64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double compare (XMM).
256 defm WriteFMulX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point multiplication (XMM).
260 …m WriteFMul64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double multiplication (XMM).
264 defm WriteFDivX : X86SchedWritePair<ReadAfterVecXLd>; // Floating point division (XMM).
268 defm WriteFDiv64X : X86SchedWritePair<ReadAfterVecXLd>; // Floating point double division (XMM).
[all …]
H A DX86InstrSSE.td198 Sched<[SchedWriteFShuffle.XMM]>;
205 Sched<[SchedWriteFShuffle.XMM]>, FoldGenData<Name#rr>;
296 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
315 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
352 SSEPackedSingle, SchedWriteFMoveLS.XMM>,
355 SSEPackedDouble, SchedWriteFMoveLS.XMM>,
358 SSEPackedSingle, SchedWriteFMoveLS.XMM>,
361 SSEPackedDouble, SchedWriteFMoveLS.XMM>,
380 SSEPackedSingle, SchedWriteFMoveLS.XMM>,
383 SSEPackedSingle, SchedWriteFMoveLS.XMM>,
[all …]
H A DX86CallingConv.td34 list<Register> XMM = [];
46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
100 // float, double, float128 --> XMM
103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
108 // __m128, __m128i, __m128d --> XMM
111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
182 // float, double, float128 --> XMM
184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
186 // __m128, __m128i, __m128d --> XMM
[all …]
H A DX86ScheduleZnver3.td912 defm : Zn3WriteResXMMPair<WriteFAddX, [Zn3FPFAdd01], 3, [1], 1>; // Floating point add/sub (XMM).
916 …Zn3WriteResXMMPair<WriteFAdd64X, [Zn3FPFAdd01], 3, [1], 1>; // Floating point double add/sub (XMM).
920 defm : Zn3WriteResXMMPair<WriteFCmpX, [Zn3FPFMul01], 1, [1], 1>; // Floating point compare (XMM).
924 …Zn3WriteResXMMPair<WriteFCmp64X, [Zn3FPFMul01], 1, [1], 1>; // Floating point double compare (XMM).
930 …: Zn3WriteResXMMPair<WriteFMulX, [Zn3FPFMul01], 3, [1], 1>; // Floating point multiplication (XMM).
934 …eResXMMPair<WriteFMul64X, [Zn3FPFMul01], 3, [1], 1>; // Floating point double multiplication (XMM).
938 defm : Zn3WriteResXMMPair<WriteFDivX, [Zn3FPFDiv], 11, [3], 1>; // Floating point division (XMM).
942 …Zn3WriteResXMMPair<WriteFDiv64X, [Zn3FPFDiv], 13, [5], 1>; // Floating point double division (XMM).
946 …m : Zn3WriteResXMMPair<WriteFSqrtX, [Zn3FPFDiv], 15, [5], 1>; // Floating point square root (XMM).
950 …riteResXMMPair<WriteFSqrt64X, [Zn3FPFDiv], 21, [9], 1>; // Floating point double square root (XMM).
[all …]
H A DX86InstrFMA.td106 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
108 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
110 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>;
477 VEX_W, Sched<[sched.XMM]>;
484 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold, sched.XMM.ReadAfterFold]>;
491 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold,
496 sched.XMM.ReadAfterFold]>;
530 Sched<[sched.XMM]>, FoldGenData<NAME#rr>;
H A DX86SchedBroadwell.td246 defm : BWWriteResPair<WriteFAddX, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub (XMM).
250 …m : BWWriteResPair<WriteFAdd64X, [BWPort1], 3, [1], 1, 5>; // Floating point double add/sub (XMM).
255 defm : BWWriteResPair<WriteFCmpX, [BWPort1], 3, [1], 1, 5>; // Floating point compare (XMM).
259 …m : BWWriteResPair<WriteFCmp64X, [BWPort1], 3, [1], 1, 5>; // Floating point double compare (XMM).
267 …m : BWWriteResPair<WriteFMulX, [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
271 …riteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
276 …teResPair<WriteFDivX, [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
280 …teResPair<WriteFDiv64X, [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
286 …esPair<WriteFSqrtX, [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
291 …WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
[all …]
H A DX86InstrAVX512.td794 // vinsertps - insert f32 to XMM
801 EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>;
809 Sched<[SchedWriteFShuffle.XMM.Folded, SchedWriteFShuffle.XMM.ReadAfterFold]>;
1125 // vextractps - extract 32 bits from XMM
1986 defm Z128 : WriteFVarBlendask<opc, OpcodeStr, sched.XMM, VTInfo.info128>,
1987 WriteFVarBlendask_rmb<opc, OpcodeStr, sched.XMM, VTInfo.info128>,
2001 defm Z128 : WriteFVarBlendask<opc, OpcodeStr, sched.XMM, VTInfo.info128>,
2162 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, sched.XMM,
2178 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, sched.XMM,
2354 sched.XMM, VTInfo.info128, NAME>, EVEX_V128;
[all …]
H A DX86RegisterInfo.td211 // XMM Registers, used by the various SSE instruction set extensions.
255 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
256 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
264 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
536 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
598 def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>;
H A DREADME-X86-64.txt172 1. We shouldn't spill the XMM registers because we only call va_arg with "int".
181 2. If we know nothing more than 64 bits wide is read from the XMM registers,
/netbsd-src/external/cddl/osnet/dev/dtrace/x86/
H A Ddis_tables.c193 XMM, /* SIMD xmm/mem -> xmm */ enumerator
663 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XM…
664 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",X…
670 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd…
671 … TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
683 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
684 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
685 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XM…
686 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
688 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packs…
[all …]
/netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/internal/array/
H A Doperations.d99 cast(void) __simd_sto(XMM.STOUPS, *cast(vec*) p, val); in version()
101 cast(void) __simd_sto(XMM.STOUPD, *cast(vec*) p, val); in version()
103 cast(void) __simd_sto(XMM.STODQU, *cast(vec*) p, val); in version()
114 return cast(typeof(return)) __simd(XMM.LODUPS, *cast(const vec*) p); in version()
116 return cast(typeof(return)) __simd(XMM.LODUPD, *cast(const vec*) p); in version()
118 return cast(typeof(return)) __simd(XMM.LODDQU, *cast(const vec*) p); in version()
/netbsd-src/crypto/external/bsd/openssl/dist/doc/man3/
H A DOPENSSL_ia32cap.pod32 =item bit #24, FXSR bit, denoting availability of XMM registers;
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
69 enable XMM registers. Historically address of the capability vector copy
/netbsd-src/crypto/external/bsd/openssl.old/dist/doc/man3/
H A DOPENSSL_ia32cap.pod32 =item bit #24, FXSR bit, denoting availability of XMM registers;
66 clearing bit #24 disables SSE2 code operating on 128-bit XMM register
69 enable XMM registers. Historically address of the capability vector copy
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Di386-dis-evex-w.h458 { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
463 { "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
H A Di386-dis-evex-prefix.h457 { "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
H A DChangeLog-20202657 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2661 (vmovq): Drop NoRex64 from XMM/XMM variants.
2796 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
3067 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Di386-dis-evex-w.h448 { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
453 { "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
H A Di386-dis-evex-prefix.h399 { "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
H A DChangeLog-20202657 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2661 (vmovq): Drop NoRex64 from XMM/XMM variants.
2796 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
3067 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
/netbsd-src/external/gpl3/gcc/dist/libsanitizer/tsan/
H A Dtsan_rtl_amd64.S45 # All XMM registers are caller-saved.
163 # All XMM registers are caller-saved.
/netbsd-src/external/gpl3/gdb/dist/opcodes/
H A DChangeLog-20202657 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2661 (vmovq): Drop NoRex64 from XMM/XMM variants.
2796 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
3067 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.

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