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Searched refs:WriteI (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveInterval.cpp1148 OS << " updater with gap = " << (ReadI - WriteI) in print()
1151 for (const auto &S : make_range(LR->begin(), WriteI)) in print()
1195 WriteI = ReadI = LR->begin(); in add()
1205 if (ReadI != WriteI) in add()
1208 if (ReadI == WriteI) in add()
1209 ReadI = WriteI = LR->find(Seg.start); in add()
1212 *WriteI++ = *ReadI++; in add()
1242 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1243 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1248 if (WriteI != ReadI) { in add()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td51 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
201 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
205 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
209 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
225 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
229 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
235 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
264 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA53.td60 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
162 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
166 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
203 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA55.td64 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
183 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
188 def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
192 def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
207 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
211 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
217 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
229 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedThunderX2T99.td416 def : WriteRes<WriteI, [THX2T99I012]> {
422 def : InstRW<[WriteI],
435 def : InstRW<[WriteI], (instrs COPY)>;
582 // NOTE: Handled by WriteI.
599 // NOTE: Handled by WriteLD, WriteI.
720 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
721 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
722 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64SchedKryo.td65 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
129 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA57.td74 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
130 def : InstRW<[WriteI], (instrs COPY)>;
145 SchedVar<NoSchedPred, [WriteI]>]>;
602 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
608 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
615 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
621 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
631 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
H A DAArch64SchedA64FX.td812 def : WriteRes<WriteI, [A64FXGI2456]> {
817 def : InstRW<[WriteI],
830 def : InstRW<[WriteI], (instrs COPY)>;
972 // NOTE: Handled by WriteI.
989 // NOTE: Handled by WriteLD, WriteI.
1109 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRBpost)>;
1110 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRDpost)>;
1111 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRHpost)>;
1112 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRQpost)>;
1113 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
H A DAArch64SchedFalkor.td70 def : WriteRes<WriteI, []> { let Unsupported = 1; }
H A DAArch64SchedCyclone.td127 SchedVar<NoSchedPred, [WriteI]>]>;
151 def : WriteRes<WriteI, [CyUnitI]>;
293 def : InstRW<[WriteI], (instrs ISB)>;
360 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
H A DAArch64SchedThunderX3T110.td676 def : WriteRes<WriteI, [THX3T110I0123]> {
682 def : InstRW<[WriteI],
695 def : InstRW<[WriteI], (instrs COPY)>;
842 // NOTE: Handled by WriteI.
859 // NOTE: Handled by WriteLD, WriteI.
953 def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteI],
967 def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteI],
H A DAArch64SchedTSV110.td55 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
117 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64InstrFormats.td1927 Sched<[WriteI, ReadI]> {
1963 Sched<[WriteI, ReadI]> {
1989 Sched<[WriteI, ReadI, ReadI]> {
2013 Sched<[WriteI, ReadI, ReadI]> {
2042 Sched<[WriteI, ReadI, ReadI]> {
2269 Sched<[WriteI]> {
2333 Sched<[WriteI, ReadI]> {
2364 Sched<[WriteI, ReadI]> {
2390 Sched<[WriteI, ReadI, ReadI]>;
2806 Sched<[WriteI, ReadI]> {
[all …]
H A DAArch64SchedExynosM3.td197 def : SchedAlias<WriteI, M3WriteA1>;
H A DAArch64SchedExynosM5.td543 def : SchedAlias<WriteI, M5WriteA1W>;
H A DAArch64SchedExynosM4.td510 def : SchedAlias<WriteI, M4WriteA1>;
H A DAArch64InstrInfo.td2287 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveInterval.h931 LiveRange::iterator WriteI; variable