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Searched refs:WREG8 (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_mxgpu_ai.c42 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_ai_mailbox_send_ack()
47 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_ai_mailbox_set_valid()
H A Damdgpu_mxgpu_nv.c42 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_nv_mailbox_send_ack()
47 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_nv_mailbox_set_valid()
H A Damdgpu.h1049 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_legacy_tv.c294 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
296 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
H A Dradeon_r100.c2905 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2918 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3843 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3856 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
H A Dradeon_display.c76 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
213 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
H A Dradeon.h2582 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v)) macro
2587 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro