Searched refs:VectorWidth (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | ScalarizeMaskedMemIntrin.cpp | 108 static unsigned adjustForEndian(const DataLayout &DL, unsigned VectorWidth, in adjustForEndian() argument 110 return DL.isBigEndian() ? VectorWidth - 1 - Idx : Idx; in adjustForEndian() 179 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements(); in scalarizeMaskedLoad() local 185 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) { in scalarizeMaskedLoad() 200 if (VectorWidth != 1) { in scalarizeMaskedLoad() 201 Type *SclrMaskTy = Builder.getIntNTy(VectorWidth); in scalarizeMaskedLoad() 205 for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) { in scalarizeMaskedLoad() 214 if (VectorWidth != 1) { in scalarizeMaskedLoad() 216 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedLoad() 218 Builder.getIntN(VectorWidth, 0)); in scalarizeMaskedLoad() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MVETailPredication.cpp | 214 int VectorWidth = in IsSafeActiveMask() local 216 if (VectorWidth != 4 && VectorWidth != 8 && VectorWidth != 16) in IsSafeActiveMask() 242 (ConstElemCount->getZExtValue() + VectorWidth - 1) / VectorWidth; in IsSafeActiveMask() 266 auto *VW = SE->getSCEV(ConstantInt::get(TripCount->getType(), VectorWidth)); in IsSafeActiveMask() 269 SE->getSCEV(ConstantInt::get(TripCount->getType(), VectorWidth - 1))); in IsSafeActiveMask() 280 dbgs() << "ARM TP: - VecWidth = " << VectorWidth << "\n"; in IsSafeActiveMask() 339 if (VectorWidth == StepValue) in IsSafeActiveMask() 343 << " doesn't match vector width " << VectorWidth << "\n"); in IsSafeActiveMask() 353 unsigned VectorWidth = in InsertVCTPIntrinsic() local 364 ConstantInt *Factor = ConstantInt::get(cast<IntegerType>(Ty), VectorWidth); in InsertVCTPIntrinsic() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 614 int VectorWidth = VT.getSizeInBits(); in group2Shuffle() local 617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1470 unsigned VectorWidth = 0; in translateGetElementPtr() local 1472 VectorWidth = cast<FixedVectorType>(VT)->getNumElements(); in translateGetElementPtr() 1476 if (VectorWidth && !PtrTy.isVector()) { in translateGetElementPtr() 1478 MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg) in translateGetElementPtr() 1480 PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth); in translateGetElementPtr() 1514 if (!IdxTy.isVector() && VectorWidth) { in translateGetElementPtr()
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| /netbsd-src/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| H A D | Attr.td | 2641 let Args = [UnsignedArgument<"VectorWidth">];
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 5095 if (unsigned VectorWidth = getContext().BuiltinInfo.getRequiredVectorWidth(BuiltinID)) in EmitBuiltinExpr() local 5096 LargestVectorWidth = std::max(LargestVectorWidth, VectorWidth); in EmitBuiltinExpr()
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