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Searched refs:VecReg (Results 1 – 8 of 8) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp679 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair() argument
680 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
681 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
684 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair() argument
685 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
688 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle() argument
689 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); in IsVecRegSingle()
H A DHexagonMCInstrInfo.h354 bool IsVecRegSingle(unsigned VecReg);
355 bool IsVecRegPair(unsigned VecReg);
356 bool IsReverseVecRegPair(unsigned VecReg);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp264 Register VecReg, unsigned LaneIdx,
3226 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
3227 LLT VecTy = MRI.getType(VecReg); in selectReduction()
3234 {VecReg, VecReg}); in selectReduction()
3752 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
3769 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
3770 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
3779 Register InsertReg = VecReg; in emitExtractVectorElt()
3785 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
3795 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp1814 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1817 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
1821 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1823 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1824 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
1842 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1855 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1857 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1858 .addReg(VecReg, in expandPostRAPseudo()
1882 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
[all …]
H A DAMDGPURegisterBankInfo.cpp1902 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1910 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1946 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
1984 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
1992 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2033 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
H A DAMDGPUInstructionSelector.cpp2691 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
2700 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2716 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2742 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
2752 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp3636 unsigned VecReg, in computeIndirectRegAndOffset() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2261 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2262 LLT VecTy = MRI.getType(VecReg); in widenScalar()
2286 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2287 LLT VecTy = MRI.getType(VecReg); in widenScalar()