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Searched refs:VecRC (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp139 const auto &VecRC = *MRI.getRegClass(VecR); in runOnMachineFunction() local
140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment, in runOnMachineFunction()
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID in runOnMachineFunction()
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
H A DHexagonVLIWPacketizer.cpp879 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToDotNew() local
880 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass) in canPromoteToDotNew()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3336 const TargetRegisterClass *VecRC = nullptr; in emitINSERT_DF_VIDX() local
3352 VecRC = &Mips::MSA128BRegClass; in emitINSERT_DF_VIDX()
3358 VecRC = &Mips::MSA128HRegClass; in emitINSERT_DF_VIDX()
3364 VecRC = &Mips::MSA128WRegClass; in emitINSERT_DF_VIDX()
3370 VecRC = &Mips::MSA128DRegClass; in emitINSERT_DF_VIDX()
3375 Register Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3393 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3399 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2711 const TargetRegisterClass *VecRC = TRI.getRegClassForTypeOnBank(VecTy, *VecRB, in selectG_INSERT_VECTOR_ELT() local
2716 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2717 !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2726 std::tie(IdxReg, SubReg) = computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, in selectG_INSERT_VECTOR_ELT()
2750 TII.getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp3700 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg); in emitIndirectSrc() local
3705 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset); in emitIndirectSrc()
3721 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true); in emitIndirectSrc()
3756 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true); in emitIndirectSrc()
3786 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst() local
3793 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC, in emitIndirectDst()
3822 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in emitIndirectDst()
3832 TRI.getRegSizeInBits(*VecRC), 32, false); in emitIndirectDst()
3848 Register PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst()
3857 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false); in emitIndirectDst()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp3771 const TargetRegisterClass *VecRC = in emitExtractVectorElt() local
3773 if (!VecRC) { in emitExtractVectorElt()