Searched refs:Vec2 (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/clang/lib/AST/ |
| H A D | ASTStructuralEquivalence.cpp | 809 const auto *Vec2 = cast<DependentSizedExtVectorType>(T2); in IsStructurallyEquivalent() local
811 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
814 Vec2->getElementType())) in IsStructurallyEquivalent()
821 const auto *Vec2 = cast<DependentVectorType>(T2); in IsStructurallyEquivalent() local
822 if (Vec1->getVectorKind() != Vec2->getVectorKind()) in IsStructurallyEquivalent()
825 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
828 Vec2->getElementType())) in IsStructurallyEquivalent()
836 const auto *Vec2 = cast<VectorType>(T2); in IsStructurallyEquivalent() local
838 Vec2->getElementType())) in IsStructurallyEquivalent()
840 if (Vec1->getNumElements() != Vec2->getNumElements()) in IsStructurallyEquivalent()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1832 SDValue Vec2; in ExpandBVWithShuffles() local
1834 Vec2 = IntermedVals[1].first; in ExpandBVWithShuffles()
1836 Vec2 = DAG.getUNDEF(VT); in ExpandBVWithShuffles()
1845 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBVWithShuffles()
1947 SDValue Vec2; in ExpandBUILD_VECTOR() local
1949 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
1951 Vec2 = DAG.getUNDEF(VT); in ExpandBUILD_VECTOR()
1954 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBUILD_VECTOR()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 299 Value *Vec2 = nullptr; in isShuffle() local
325 else if (!Vec2 || Vec2 == Vec) in isShuffle()
326 Vec2 = Vec; in isShuffle()
340 if (CommonShuffleMode == Select && Vec2) in isShuffle()
344 return Vec2 ? TargetTransformInfo::SK_PermuteTwoSrc in isShuffle()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 4355 Value *Vec1, *Vec2, *Mask; in parseFunctionBody() local
4357 popValue(Record, OpNum, NextValueNo, Vec1->getType(), Vec2)) in parseFunctionBody()
4362 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy()) in parseFunctionBody()
4365 I = new ShuffleVectorInst(Vec1, Vec2, Mask); in parseFunctionBody()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10618 SDValue Vec2 = Op2.getOperand(0); in performFMACombine() local
10643 if (Vec1 == Vec2 || Vec3 == Vec4) in performFMACombine()
10646 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16) in performFMACombine()
10649 if ((Vec1 == Vec3 && Vec2 == Vec4) || in performFMACombine()
10650 (Vec1 == Vec4 && Vec2 == Vec3)) { in performFMACombine()
10651 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrPrefix.td | 1603 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1619 Extracts.Vec2>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | ProgrammersManual.rst | 1705 PackedVector<State, 2> Vec2;
1706 Vec2.push_back(SecondCondition);
1708 Vec1 |= Vec2;
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