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Searched refs:Vd (Results 1 – 22 of 22) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
H A DARMInstrCDE.td299 iname#"\t$coproc, $Vd, $imm", params.Cstr> {
313 bits<5> Vd;
315 let Inst{22} = Vd{0};
316 let Inst{15-12} = Vd{4-1};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
326 let Inst{15-12} = Vd{3-0};
360 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {
374 bits<5> Vd;
377 let Inst{15-12} = Vd{4-1};
[all …]
H A DARMInstrFormats.td2227 bits<5> Vd;
2231 let Inst{22} = Vd{4};
2232 let Inst{15-12} = Vd{3-0};
2297 bits<5> Vd;
2300 let Inst{15-12} = Vd{3-0};
2301 let Inst{22} = Vd{4};
2323 bits<5> Vd;
2326 let Inst{15-12} = Vd{3-0};
2327 let Inst{22} = Vd{4};
2337 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
H A DARMInstrVFP.td1765 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1778 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Daarch64-tbl.h2790 …SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZ…
2791 …SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZ…
2792 …SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZ…
2793 …SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZ…
2794 …SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZ…
2795 …SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZ…
2796 …SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZ…
2797 …SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZ…
2798 …SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZ…
2799 …SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZ…
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h2998 …SIMD_INSN ("saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZ…
2999 …SIMD_INSN ("saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZ…
3000 …SIMD_INSN ("saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZ…
3001 …SIMD_INSN ("saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZ…
3002 …SIMD_INSN ("ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZ…
3003 …SIMD_INSN ("ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZ…
3004 …SIMD_INSN ("ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZ…
3005 …SIMD_INSN ("ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZ…
3006 …SIMD_INSN ("addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZ…
3007 …SIMD_INSN ("addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZ…
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h379 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
380 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
381 Flags = Vd.kind(); in Variable()
666 Function(Variable *Vd, SExpr *Bd) in Function() argument
667 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
668 Vd->setKind(Variable::VK_Fun); in Function()
671 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
672 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
673 Vd->setKind(Variable::VK_Fun); in Function()
717 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/Analysis/
H A DThreadSafety.cpp265 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
267 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
299 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
302 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
305 void checkBeforeAfter(const ValueDecl* Vd,
1068 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
1075 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs()
1081 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1109 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1123 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td937 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
938 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
991 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))),
992 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;
995 …: Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:…
996 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>;
4149 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
4150 (NOTv8i8 V64:$Vd, V64:$Vn)>;
4151 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
4152 (NOTv16i8 V128:$Vd, V128:$Vn)>;
[all …]
H A DAArch64InstrFormats.td6167 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
6168 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
6169 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
6170 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6172 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
6173 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
6174 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
6175 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6176 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
6177 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
H A DAArch64SchedPredicates.td411 [// MOVI Vd, #0
416 // MOVI Vd, #0, LSL #0
H A DAArch64SchedA64FX.td2331 // [13] "andv $Vd, $Pg, $Zn";
2580 // [96] "eorv $Vd, $Pg, $Zn";
2610 // [107] "faddv $Vd, $Pg, $Zn";
2703 // [135] "fmaxnmv $Vd, $Pg, $Zn";
2706 // [136] "fmaxv $Vd, $Pg, $Zn";
2721 // [141] "fminnmv $Vd, $Pg, $Zn";
2724 // [142] "fminv $Vd, $Pg, $Zn";
2879 // [196] "lasta $Vd, $Pg, $Zn";
2885 // [198] "lastb $Vd, $Pg, $Zn";
3299 // [336] "orv $Vd, $Pg, $Zn";
[all …]
H A DAArch64SchedCyclone.td323 // FMOVv2f64ns Vd.2d, #0.0
332 // ORR.16b Vd,Vn,Vn
633 // Vd is read 5 cycles after issuing the vector load.
H A DSVEInstrFormats.td4636 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
4637 asm, "\t$Vd, $Pg, $Zn",
4641 bits<5> Vd;
4650 let Inst{4-0} = Vd;
6040 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
6041 asm, "\t$Vd, $Pg, $Zn",
6045 bits<5> Vd;
6054 let Inst{4-0} = Vd;
7371 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
7372 asm, "\t$Vd, $Pg, $Zn",
[all …]
/netbsd-src/crypto/external/bsd/heimdal/dist/lib/hx509/data/
H A Dtest-pw.key34 N+4tGdP1v8+Vd+BipaQAXor6kd1pn+oywKttx6eZE1jHHnZzJpX6VrqwnIdxtlEJ
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1593 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1597 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1598 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1603 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1606 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1617 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1621 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1622 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1628 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1631 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/netbsd-src/external/bsd/file/dist/tests/
H A DHWP97.hwp.testfile8 …L�rQ9L�#������ 9�}\��q]ɰ^6�G�����] ��Փ3Q׻�"����l����a�ˤ�&W:Ln�VdR�u�;*g�^���|�N���…
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1191 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1192 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1193 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1194 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
H A DHexagonPseudo.td468 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
/netbsd-src/sys/dev/microcode/wi/
H A Desecsym83 ���!�dN�`�e��������"`<x��*b�'���܄'�Z`Fd����܄��ڂ����܄��`�d�������`E`VdĄ����܄��S�����`E`�dĄ��…
216 …��������d`E`VbƂ���c��`Tc����Є��`�bƂ���c��`�c����Є��`�ceD��aE`�c��`VdĄ����`A����`Tc������…
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-objdump/
H A DMachODump.cpp10137 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
10138 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()
/netbsd-src/games/fortune/datfiles/
H A Dfortunes2-o.real12902 Vd, n: