| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 50 unsigned ValueReg, unsigned Address,
56 unsigned ValueReg, unsigned Address,
246 unsigned ValueReg, unsigned Address,
254 unsigned ValueReg, unsigned Address,
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| H A D | SIRegisterInfo.cpp | 921 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
935 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
936 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1023 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1041 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
1145 ? ValueReg in buildSpillLoadStore()
1146 : Register(getSubReg(ValueReg, in buildSpillLoadStore()
1167 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore()
1168 : ValueReg; in buildSpillLoadStore()
1173 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
[all …]
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| H A D | R600InstrInfo.cpp | 1093 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1095 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1100 unsigned ValueReg, unsigned Address, in buildIndirectWrite() argument
1116 AddrReg, ValueReg) in buildIndirectWrite()
1125 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1127 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectRead()
1132 unsigned ValueReg, unsigned Address, in buildIndirectRead() argument
1148 ValueReg, in buildIndirectRead()
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| H A D | SIRegisterInfo.h | 354 int Index, Register ValueReg, bool ValueIsKill,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 1286 unsigned ValueReg = getRegForValue(Store->getValueOperand()); in selectStore() local
1287 if (ValueReg == 0) in selectStore()
1290 ValueReg = maskI1Value(ValueReg, Store->getValueOperand()); in selectStore()
1296 MIB.addReg(ValueReg); in selectStore()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode() local
185 const LLT Ty = MRI.getType(ValueReg); in selectLoadStoreOpCode()
191 if (isRegInGprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
221 if (isRegInFprb(ValueReg, MRI)) { in selectLoadStoreOpCode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11175 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary() local
11176 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
11178 MI.getOperand(3).setReg(ValueReg); in EmitPartwordAtomicBinary()
11320 unsigned ValueReg = SReg; in EmitPartwordAtomicBinary() local
11323 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11324 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
11329 .addReg(ValueReg); in EmitPartwordAtomicBinary()
11330 ValueReg = ValueSReg; in EmitPartwordAtomicBinary()
11335 .addReg(ValueReg); in EmitPartwordAtomicBinary()
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