Searched refs:VT0 (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURewriteOutArguments.cpp | 192 auto *VT0 = dyn_cast<FixedVectorType>(Ty0); in isVec3ToVec4Shuffle() local 194 if (!VT0 || !VT1) in isVec3ToVec4Shuffle() 197 if (VT0->getNumElements() != 3 || in isVec3ToVec4Shuffle() 201 return DL->getTypeSizeInBits(VT0->getElementType()) == in isVec3ToVec4Shuffle()
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| /netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/sys/posix/ |
| H A D | termios.d | 1018 enum VT0 = 0x0000000; // 0000000 in version() local 1053 enum VT0 = 0x00000000; in version() local 1225 enum VT0 = 0x0000000; in version() local 1260 enum VT0 = 0x0000000; // 0000000 in version() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 75 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local 77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering() 78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering() 79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering() 80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4306 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTMask() local 4308 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTMask() 4316 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask() 4317 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask() 4326 MaskVT = VT0; in WidenVSELECTMask() 4329 SETCC0 = convertMask(SETCC0, VT0, MaskVT); in WidenVSELECTMask()
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| H A D | DAGCombiner.cpp | 9405 EVT VT0 = N0.getValueType(); in visitSELECT() local 9422 if (VT0 == MVT::i1) { in visitSELECT() 9544 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 36392 EVT VT0 = BC0.getValueType(); in canonicalizeShuffleMaskWithHorizOp() local 36394 if (VT0.getSizeInBits() != RootSizeInBits || llvm::any_of(BC, [&](SDValue V) { in canonicalizeShuffleMaskWithHorizOp() 36395 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp() 36411 int NumElts = VT0.getVectorNumElements(); in canonicalizeShuffleMaskWithHorizOp() 36412 int NumLanes = VT0.getSizeInBits() / 128; in canonicalizeShuffleMaskWithHorizOp() 36431 return DAG.getUNDEF(VT0); in canonicalizeShuffleMaskWithHorizOp() 36433 return getZeroVector(VT0.getSimpleVT(), Subtarget, DAG, DL); in canonicalizeShuffleMaskWithHorizOp() 36447 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp() 36477 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp() 36493 if (Mask.size() == VT0.getVectorNumElements()) { in canonicalizeShuffleMaskWithHorizOp() [all …]
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