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Searched refs:VOffset (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp730 unsigned VOffset = 0; in getMachineOpValue() local
749 ++VOffset; in getMachineOpValue()
771 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3690 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
3701 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferStore()
3733 .addUse(VOffset) // voffset in legalizeBufferStore()
3773 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
3791 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferLoad()
3836 .addUse(VOffset) // voffset in legalizeBufferLoad()
3974 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferAtomic() local
3982 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferAtomic()
4001 .addUse(VOffset) // voffset in legalizeBufferAtomic()
H A DAMDGPUInstructionSelector.cpp2942 MachineOperand &VOffset = MI.getOperand(4); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
2946 bool HasVOffset = !isOperandImmEqual(VOffset, 0, *MRI); in selectAMDGPU_BUFFER_ATOMIC_FADD()
2984 .addReg(VOffset.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
2991 I.add(VOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3597 if (Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) { in selectGlobalSAddr() local
3602 MIB.addReg(VOffset); in selectGlobalSAddr()
3621 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
3623 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32), VOffset) in selectGlobalSAddr()
3628 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
H A DAMDGPUISelDAGToDAG.cpp213 SDValue &VOffset, SDValue &Offset) const;
1782 SDValue &VOffset, in SelectGlobalSAddr() argument
1812 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
1841 VOffset = ZextRHS; in SelectGlobalSAddr()
1849 VOffset = ZextLHS; in SelectGlobalSAddr()
1869 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
H A DAMDGPURegisterBankInfo.cpp1450 Register VOffset; in applyMappingSBufferLoad() local
1454 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
1496 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
1764 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
1769 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
1771 const bool Offen = !isZero(VOffset, MRI); in selectStoreIntrinsic()
1800 MIB.addUse(VOffset); in selectStoreIntrinsic()
H A DSIISelLowering.cpp6733 static unsigned getBufferOffsetForMMO(SDValue VOffset, in getBufferOffsetForMMO() argument
6738 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in getBufferOffsetForMMO()
6747 return cast<ConstantSDNode>(VOffset)->getSExtValue() + in getBufferOffsetForMMO()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp38002 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
38006 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()