| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | AMDGPUInstructionSyntax.rst | 125 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
134 Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
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| H A D | AMDGPUUsage.rst | 11563 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
11567 * _e32 for 32-bit VOP1/VOP2/VOPC
11572 VOP1/VOP2/VOP3/VOPC examples:
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | VOPCInstructions.td | 44 // VOPC classes
47 // VOPC instructions are a special case because for the 32-bit
55 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
96 let VOPC = 1;
130 // This class is used only with VOPC instructions. Use $sdst for out operand
887 // Encoding used for VOPC instructions encoded as VOP3 differs from
888 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1004 // Encoding used for VOPC instructions encoded as VOP3 differs from
1005 // VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
1234 // Encoding used for VOPC instructions encoded as VOP3
[all …]
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| H A D | SIInstrFormats.td | 30 field bit VOPC = 0;
156 let TSFlags{9} = VOPC;
223 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| H A D | SIInstrInfo.td | 1449 SDWAVopcDst, // VOPC
1814 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1832 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1846 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1912 ""); // use $sdst for VOPC
1936 " vcc", // use vcc token as dst for VOPC instructioins
1953 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1965 "$sdst", // VOPC
1981 … " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
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| H A D | SISchedule.td | 68 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| H A D | SIInstrInfo.h | 444 return MI.getDesc().TSFlags & SIInstrFlags::VOPC; in isVOPC()
448 return get(Opcode).TSFlags & SIInstrFlags::VOPC; in isVOPC()
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| H A D | SIDefines.h | 34 VOPC = 1 << 9, enumerator
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| H A D | AMDGPU.td | 398 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
410 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
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| H A D | VOPInstructions.td | 436 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3243 (SIInstrFlags::VOPC | in validateConstantBusLimitations()
3785 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
8101 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()
8134 } else if (BasicInstType == SIInstrFlags::VOPC && in cvtSDWA()
8177 case SIInstrFlags::VOPC: in cvtSDWA()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 590 if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) && in printOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/ |
| H A D | AMDGPUAsmGFX7.rst | 1148 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX8.rst | 1433 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX9.rst | 1686 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX90a.rst | 1649 VOPC section in Instructions
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| H A D | AMDGPUAsmGFX10.rst | 1946 VOPC section in Instructions
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