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Searched refs:VE (Results 1 – 25 of 110) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp57 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
58 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
66 VE::SW63};
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} in VEInstrInfo()
98 using namespace llvm::VE; in isUncondBranchOpcode()
113 using namespace llvm::VE; in isCondBranchOpcode()
125 using namespace llvm::VE; in isIndirectBranchOpcode()
238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
254 opc[0] = VE::BRCFWir; in insertBranch()
255 opc[1] = VE::BRCFWrr; in insertBranch()
257 opc[0] = VE::BRCFLir; in insertBranch()
258 opc[1] = VE::BRCFLrr; in insertBranch()
262 opc[0] = VE::BRCFSir; in insertBranch()
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H A DVEFrameLowering.cpp152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
153 .addReg(VE::SX11) in emitPrologueInsns()
156 .addReg(VE::SX9); in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
158 .addReg(VE::SX11) in emitPrologueInsns()
161 .addReg(VE::SX10); in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
165 .addReg(VE::SX11) in emitPrologueInsns()
168 .addReg(VE::SX15); in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
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H A DVERegisterInfo.cpp34 VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {} in VERegisterInfo()
68 VE::SX8, // Stack limit in getReservedRegs()
69 VE::SX9, // Frame pointer in getReservedRegs()
70 VE::SX10, // Link register (return address) in getReservedRegs()
71 VE::SX11, // Stack pointer in getReservedRegs()
74 VE::SX12, // Outer register in getReservedRegs()
75 VE::SX13, // Id register for dynamic linker in getReservedRegs()
77 VE::SX14, // Thread pointer in getReservedRegs()
78 VE::SX15, // Global offset table register in getReservedRegs()
79 VE::SX16, // Procedure linkage table register in getReservedRegs()
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H A DVEFrameLowering.h60 {VE::SX17, 40}, {VE::SX18, 48}, {VE::SX19, 56}, {VE::SX20, 64}, in getCalleeSavedSpillSlots()
61 {VE::SX21, 72}, {VE::SX22, 80}, {VE::SX23, 88}, {VE::SX24, 96}, in getCalleeSavedSpillSlots()
62 {VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128}, in getCalleeSavedSpillSlots()
63 {VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160}, in getCalleeSavedSpillSlots()
64 {VE::SX33, 168}}; in getCalleeSavedSpillSlots()
H A DVEISelLowering.cpp81 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
82 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
83 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
84 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
85 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
89 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
90 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
91 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
366 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
444 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerFormalArguments()
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H A DVERegisterInfo.td1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
10 // Declarations that describe the VE register file
18 let Namespace = "VE";
26 let Namespace = "VE";
34 let Namespace = "VE";
44 let Namespace = "VE";
49 let Namespace = "VE" in {
77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
168 def I32 : RegisterClass<"VE", [i32], 32,
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H A DVEAsmPrinter.cpp86 SICInst.setOpcode(VE::SIC); in emitSIC()
94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
164 emitBinary(OutStreamer, VE::ANDrm, RS1, Imm, RD, STI); in emitANDrm()
203 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT in lowerGETGOTAndEmitMCInsts()
204 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETGOTAndEmitMCInsts()
252 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETFunPLTAndEmitMCInsts()
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H A DVE.td1 //===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
19 // VE Subtarget features.
36 // Use both VE register name matcher to accept "S0~S63" register names
43 // VE processors supported.
61 def VE : Target {
H A DVECallingConv.td1 //===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
9 // This describes the calling conventions for the VE architectures.
14 // Aurora VE
24 ///// C Calling Convention (VE ABI v2.1) /////
26 // Reference: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-ABI_v2.1.pdf
58 ///// Standard vararg C Calling Convention (VE ABI v2.1) /////
H A DCMakeLists.txt1 add_llvm_component_group(VE)
3 set(LLVM_TARGET_DEFINITIONS VE.td)
42 VE
H A DVVPInstrInfo.td9 // This file defines the VE Vector Predicated SDNodes (VVP SDNodes). VVP
11 // LLVM and the actual VE vector instructions. For example:
15 // The standard The VVP layer SDNode. The VE vector instruction.
H A DLVLGen.cpp57 return VE::NoRegister; in getVL()
78 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
91 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg); in runOnMachineBasicBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
H A DVEAsmBackend.cpp36 case VE::fixup_ve_hi32: in adjustFixupValue()
37 case VE::fixup_ve_pc_hi32: in adjustFixupValue()
38 case VE::fixup_ve_got_hi32: in adjustFixupValue()
39 case VE::fixup_ve_gotoff_hi32: in adjustFixupValue()
40 case VE::fixup_ve_plt_hi32: in adjustFixupValue()
41 case VE::fixup_ve_tls_gd_hi32: in adjustFixupValue()
42 case VE::fixup_ve_tpoff_hi32: in adjustFixupValue()
44 case VE::fixup_ve_reflong: in adjustFixupValue()
45 case VE::fixup_ve_lo32: in adjustFixupValue()
46 case VE::fixup_ve_pc_lo32: in adjustFixupValue()
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H A DVEELFObjectWriter.cpp59 case VE::fixup_ve_pc_hi32: in getRelocType()
61 case VE::fixup_ve_pc_lo32: in getRelocType()
77 case VE::fixup_ve_reflong: in getRelocType()
79 case VE::fixup_ve_hi32: in getRelocType()
81 case VE::fixup_ve_lo32: in getRelocType()
83 case VE::fixup_ve_pc_hi32: in getRelocType()
85 case VE::fixup_ve_pc_lo32: in getRelocType()
87 case VE::fixup_ve_got_hi32: in getRelocType()
89 case VE::fixup_ve_got_lo32: in getRelocType()
91 case VE::fixup_ve_gotoff_hi32: in getRelocType()
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H A DVEMCExpr.cpp137 VE::Fixups VEMCExpr::getFixupKind(VEMCExpr::VariantKind Kind) { in getFixupKind()
142 return VE::fixup_ve_reflong; in getFixupKind()
144 return VE::fixup_ve_hi32; in getFixupKind()
146 return VE::fixup_ve_lo32; in getFixupKind()
148 return VE::fixup_ve_pc_hi32; in getFixupKind()
150 return VE::fixup_ve_pc_lo32; in getFixupKind()
152 return VE::fixup_ve_got_hi32; in getFixupKind()
154 return VE::fixup_ve_got_lo32; in getFixupKind()
156 return VE::fixup_ve_gotoff_hi32; in getFixupKind()
158 return VE::fixup_ve_gotoff_lo32; in getFixupKind()
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H A DVEInstPrinter.cpp29 namespace VE { namespace
30 using namespace VE;
40 unsigned AltIdx = VE::AsmName; in printRegName()
42 if (MRI.getRegClass(VE::MISCRegClassID).contains(RegNo)) in printRegName()
43 AltIdx = VE::NoRegAltName; in printRegName()
H A DVEMCExpr.h68 VE::Fixups getFixupKind() const { return getFixupKind(Kind); } in getFixupKind()
90 static VE::Fixups getFixupKind(VariantKind Kind);
H A DVEMCTargetDesc.cpp38 unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true); in createVEMCAsmInfo()
52 InitVEMCRegisterInfo(X, VE::SX10); in createVEMCRegisterInfo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp99 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
100 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
101 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
102 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
103 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
104 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
105 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
106 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
107 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
108 VE::SW63};
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Bitcode/Writer/
H A DBitcodeWriter.cpp162 ValueEnumerator VE; member in __anon97c08c270111::ModuleBitcodeWriterBase
187 VE(M, ShouldPreserveUseListOrder), Index(Index) { in ModuleBitcodeWriterBase()
193 GlobalValueId = VE.getValues().size(); in ModuleBitcodeWriterBase()
241 return VE.getValueID(VI.getValue()); in getValueId()
777 VE.getAttributeGroups(); in writeAttributeGroupTable()
786 Record.push_back(VE.getAttributeGroupID(Pair)); in writeAttributeGroupTable()
814 Record.push_back(VE.getTypeID(Attr.getValueAsType())); in writeAttributeGroupTable()
826 const std::vector<AttributeList> &Attrs = VE.getAttributeLists(); in writeAttributeTable()
837 Record.push_back(VE.getAttributeGroupID({i, AS})); in writeAttributeTable()
849 const ValueEnumerator::TypeList &TypeList = VE.getTypes(); in writeTypeTable()
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/netbsd-src/external/gpl3/gcc/dist/libphobos/libdruntime/core/internal/
H A Dlifetime.d175 enum VE : __vector(double[4]) enum
180 const VE expected = VE.a;
181 VE dst = VE.b;
182 shared VE sharedDst = VE.b;
187 assert(memcmp(&expected, &dst, VE.sizeof) == 0);
188 assert(memcmp(&expected, cast(void*) &sharedDst, VE.sizeof) == 0);
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DVE.def8 // - System V Application Binary Interface - VE Architecture
10 // - ELF Handling For Thread-Local Storage - VE Architecture
/netbsd-src/external/apache2/llvm/dist/clang/lib/Serialization/
H A DASTWriter.cpp6149 for (Expr *VE : C->varlists()) in VisitOMPInitClause()
6150 Record.AddStmt(VE); in VisitOMPInitClause()
6190 for (auto *VE : C->varlists()) { in VisitOMPPrivateClause() local
6191 Record.AddStmt(VE); in VisitOMPPrivateClause()
6193 for (auto *VE : C->private_copies()) { in VisitOMPPrivateClause() local
6194 Record.AddStmt(VE); in VisitOMPPrivateClause()
6202 for (auto *VE : C->varlists()) { in VisitOMPFirstprivateClause() local
6203 Record.AddStmt(VE); in VisitOMPFirstprivateClause()
6205 for (auto *VE : C->private_copies()) { in VisitOMPFirstprivateClause() local
6206 Record.AddStmt(VE); in VisitOMPFirstprivateClause()
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dvec-common.md189 [(match_operand:VE 0 "s_register_operand")
190 (match_operand:VE 1 "s_register_operand")
191 (match_operand:VE 2 "s_register_operand")
192 (match_operand:VE 3 "s_register_operand")]

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