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Searched refs:VA (Results 1 – 25 of 171) sorted by relevance

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/netbsd-src/sys/arch/x86/include/
H A Dpte.h60 #define pl1_pi(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT) argument
61 #define pl2_pi(VA) (((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT) argument
62 #define pl3_pi(VA) (((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT) argument
63 #define pl4_pi(VA) (((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT) argument
70 #define pl1_i(VA) (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT) argument
71 #define pl2_i(VA) (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT) argument
72 #define pl3_i(VA) (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT) argument
73 #define pl4_i(VA) (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT) argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA, in assign() argument
29 if (VA.isRegLoc()) { in assign()
30 assignValueToReg(VReg, VA, VT); in assign()
31 } else if (VA.isMemLoc()) { in assign()
32 assignValueToAddress(VReg, VA); in assign()
97 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
100 Register getStackAddress(const CCValAssign &VA,
103 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
114 MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) { in buildLoad() argument
116 Register Addr = getStackAddress(VA, MMO); in buildLoad()
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H A DMipsCallLowering.h47 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
49 virtual Register getStackAddress(const CCValAssign &VA,
52 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
56 const CCValAssign &VA) = 0;
H A DMipsFastISel.cpp1153 CCValAssign &VA = ArgLocs[i]; in processCallArgs() local
1154 const Value *ArgVal = CLI.OutVals[VA.getValNo()]; in processCallArgs()
1155 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs()
1160 VA.convertToReg(Mips::F12); in processCallArgs()
1163 VA.convertToReg(Mips::D6_64); in processCallArgs()
1165 VA.convertToReg(Mips::D6); in processCallArgs()
1170 VA.convertToReg(Mips::F14); in processCallArgs()
1173 VA.convertToReg(Mips::D7_64); in processCallArgs()
1175 VA.convertToReg(Mips::D7); in processCallArgs()
1181 VA.isMemLoc()) { in processCallArgs()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp112 CCValAssign &VA) override { in assignValueToReg()
113 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
114 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
116 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size"); in assignValueToReg()
117 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
125 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
129 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
131 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(), in assignValueToAddress()
140 CCValAssign VA = VAs[0]; in assignCustomValue() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td127 InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
155 InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
166 InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/
177 InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
217 InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
239 InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/
245 InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/
251 InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/
272 InstrItinData <tc_540c3da3, /*SLOT0,VA*/
277 InstrItinData <tc_54a0dc47, /*SLOT0,STORE,VA*/
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp262 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
266 switch (VA.getLocInfo()) { in LowerCall()
272 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
275 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
278 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
284 if (VA.isRegLoc()) { in LowerCall()
285 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
287 assert(VA.isMemLoc() && "Must be register or memory argument."); in LowerCall()
292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall()
376 const CCValAssign &VA = RVLocs[i]; in lowerCallResult() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp232 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
237 if (VA.needsCustom()) { in LowerReturn_32()
238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
252 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
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/netbsd-src/share/misc/
H A Dzipcodes8217 20120:Centreville, VA
8218 20121:Centreville, VA
8992 22001:Aldie, VA
8993 22002:Amissville, VA
8994 22003:Annandale, VA
8995 22010:Arcola, VA
8996 22011:Ashburn, VA
8997 22012:Bluemont, VA
8998 22013:Bristow, VA
8999 22014:Broad Run, VA
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/netbsd-src/sys/uvm/
H A Duvm_map.h84 #define UVM_MAP_CLIP_START(MAP,ENTRY,VA) { \ argument
85 if ((VA) > (ENTRY)->start && (VA) < (ENTRY)->end) { \
86 uvm_map_clip_start(MAP,ENTRY,VA); \
97 #define UVM_MAP_CLIP_END(MAP,ENTRY,VA) { \ argument
98 if ((VA) > (ENTRY)->start && (VA) < (ENTRY)->end) { \
99 uvm_map_clip_end(MAP,ENTRY,VA); \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp622 CCValAssign &VA = ArgLocs[j]; in handleAssignments() local
623 assert(VA.getValNo() == i && "Location doesn't correspond to current arg"); in handleAssignments()
625 if (VA.needsCustom()) { in handleAssignments()
634 const MVT ValVT = VA.getValVT(); in handleAssignments()
635 const MVT LocVT = VA.getLocVT(); in handleAssignments()
676 VA = ArgLocs[j + Part]; in handleAssignments()
679 if (VA.isMemLoc() && !Flags.isByVal()) { in handleAssignments()
685 uint64_t MemSize = Handler.getStackValueStoreSize(DL, VA); in handleAssignments()
689 Handler.getStackAddress(MemSize, VA.getLocMemOffset(), MPO, Flags); in handleAssignments()
692 VA); in handleAssignments()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp69 static uint64_t getStackValueStoreSizeHack(const CCValAssign &VA) { in getStackValueStoreSizeHack() argument
70 const MVT ValVT = VA.getValVT(); in getStackValueStoreSizeHack()
72 : VA.getLocVT().getStoreSize(); in getStackValueStoreSizeHack()
150 const CCValAssign &VA) const override { in getStackValueStoreSize()
151 return getStackValueStoreSizeHack(VA); in getStackValueStoreSize()
155 CCValAssign &VA) override { in assignValueToReg()
157 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
161 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
166 LLT ValTy(VA.getValVT()); in assignValueToAddress()
167 LLT LocTy(VA.getLocVT()); in assignValueToAddress()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp247 const CCValAssign &VA) { in MatchingStackOffset() argument
316 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) { in MatchingStackOffset()
380 const CCValAssign &VA, in LowerMemArgument() argument
389 if (VA.getLocInfo() == CCValAssign::Indirect) in LowerMemArgument()
390 ValVT = VA.getLocVT(); in LowerMemArgument()
392 ValVT = VA.getValVT(); in LowerMemArgument()
396 int Offset = VA.getLocMemOffset(); in LowerMemArgument()
397 if (VA.getValVT() == MVT::i8) { in LowerMemArgument()
399 } else if (VA.getValVT() == MVT::i16) { in LowerMemArgument()
428 if (VA.getLocInfo() == CCValAssign::ZExt) { in LowerMemArgument()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp319 for (auto &VA : ArgLocs) { in LowerFormalArguments() local
320 if (VA.isRegLoc()) { in LowerFormalArguments()
322 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
334 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
339 if (VA.getLocInfo() == CCValAssign::SExt) in LowerFormalArguments()
341 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
342 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerFormalArguments()
344 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
346 if (VA.getLocInfo() != CCValAssign::Full) in LowerFormalArguments()
347 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h249 const CCValAssign &VA) const;
255 CCValAssign &VA) = 0;
262 CCValAssign &VA) = 0;
270 CCValAssign &VA) { in assignValueToAddress()
271 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, Size, MPO, VA); in assignValueToAddress()
291 uint64_t MemSize, CCValAssign &VA) const;
295 Register extendRegister(Register ValReg, CCValAssign &VA,
307 Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
311 CCValAssign &VA) override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp338 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
339 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
340 assert(!VA.needsCustom() && "Unexpected custom lowering"); in LowerReturn()
344 switch (VA.getLocInfo()) { in LowerReturn()
348 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
351 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
354 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
362 assert(VA.getLocVT() == MVT::i64); in LowerReturn()
363 assert(VA.getValVT() == MVT::f32); in LowerReturn()
376 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn()
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/netbsd-src/sys/crypto/blake2/
H A Dblake2s.c60 #define BLAKE2S_G(VA, VB, VC, VD, X, Y) do \ argument
62 (VA) = (VA) + (VB) + (X); \
63 (VD) = rotr32((VD) ^ (VA), 16); \
66 (VA) = (VA) + (VB) + (Y); \
67 (VD) = rotr32((VD) ^ (VA), 8); \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSession.cpp212 bool NativeSession::addressForVA(uint64_t VA, uint32_t &Section, in addressForVA() argument
214 uint32_t RVA = VA - getLoadAddress(); in addressForVA()
285 uint64_t VA = getVAFromSectOffset(Section, Offset); in findLineNumbersBySectOffset() local
286 return Cache.findLineNumbersByVA(VA, Length); in findLineNumbersBySectOffset()
394 bool NativeSession::moduleIndexForVA(uint64_t VA, uint16_t &ModuleIndex) const { in moduleIndexForVA() argument
396 auto Iter = AddrToModuleIndex.find(VA); in moduleIndexForVA()
429 uint64_t VA = Session.getVAFromSectOffset(C.ISect, C.Off); in parseSectionContribs() local
430 uint64_t End = VA + C.Size; in parseSectionContribs()
434 if (!AddrMap.overlaps(VA, End)) in parseSectionContribs()
435 AddrMap.insert(VA, End, C.Imod); in parseSectionContribs()
H A DNativeInlineSiteSymbol.cpp129 NativeInlineSiteSymbol::findInlineeLinesByVA(uint64_t VA, in findInlineeLinesByVA() argument
132 if (!Session.moduleIndexForVA(VA, Modi)) in findInlineeLinesByVA()
151 getLineOffset(VA - ParentAddr, SrcLineOffset, SrcFileOffset); in findInlineeLinesByVA()
170 Session.addressForVA(VA, LineSect, LineOff); in findInlineeLinesByVA()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp457 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
458 if (VA.isRegLoc()) { in LowerCCCArguments()
460 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
464 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
470 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
472 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
473 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
475 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
477 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dppc-opc.c3614 #define VA UI7 + 1 macro
3618 #define VB VA + 1
5093 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5094 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
5095 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5096 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
5097 {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}},
5098 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
5099 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
5100 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dppc-opc.c3533 #define VA UI7 + 1 macro
3537 #define VB VA + 1
4914 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4915 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
4916 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4917 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
4918 {"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}},
4919 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
4920 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
4921 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallLowering.cpp108 CCValAssign &VA) override { in assignValueToReg()
110 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
115 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
117 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
120 VA.getLocVT().getStoreSize(), in assignValueToAddress()
190 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
199 CCValAssign &VA) override { in assignValueToReg()
201 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp639 CCValAssign &VA = ArgLocs[i]; in LowerCCCArguments() local
640 if (VA.isRegLoc()) { in LowerCCCArguments()
642 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
654 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
660 if (VA.getLocInfo() == CCValAssign::SExt) in LowerCCCArguments()
662 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
663 else if (VA.getLocInfo() == CCValAssign::ZExt) in LowerCCCArguments()
665 DAG.getValueType(VA.getValVT())); in LowerCCCArguments()
667 if (VA.getLocInfo() != CCValAssign::Full) in LowerCCCArguments()
668 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp34 Register ValVReg, CCValAssign &VA) { in extendRegisterMin32() argument
35 if (VA.getLocVT().getSizeInBits() < 32) { in extendRegisterMin32()
41 return Handler.extendRegister(ValVReg, VA); in extendRegisterMin32()
58 MachinePointerInfo &MPO, CCValAssign &VA) override { in assignValueToAddress()
63 CCValAssign &VA) override { in assignValueToReg()
64 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg()
106 CCValAssign &VA) override { in assignValueToReg()
109 if (VA.getLocVT().getSizeInBits() < 32) { in assignValueToReg()
117 buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT())); in assignValueToReg()
122 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
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