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Searched refs:V0 (Results 1 – 25 of 134) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp76 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
116 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
143 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
144 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
146 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) in initGlobalBaseReg()
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
H A DMipsRegisterInfo.td89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
123 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
286 V0, V1, A0, A1, A2, A3,
306 V0, V1, A0, A1, A2, A3,
322 V0, V1, A0, A1, A2, A3)>;
330 V0, V1, A0, A1, A2, A3)>;
338 V0, V1,
368 V0, V1, A0, A1, A2, A3,
374 V0, V1, A0, A1, A2, A3,
H A DMipsCallingConv.td99 // i32 are returned in registers V0, V1, A0, A1, unless the original return
102 CCAssignToReg<[V0, V1, A0, A1]>>>,
269 // except for AT, V0 and T9, are available to be used as argument registers.
315 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
385 CalleeSavedRegs<(add V0, V1, FP,
/netbsd-src/external/gpl2/groff/dist/src/roff/troff/
H A Ddiv.cpp57 : prev(0), nm(s), vertical_position(V0), high_water_mark(V0), in diversion()
60 marked_place(V0) in diversion()
70 : pre_extra(V0), post_extra(V0), pre(vs), post(post_vs) in vertical_size()
80 if (n < V0) { in set_vertical_size()
90 if (n < V0) in set_vertical_size()
322 else if (n + vertical_position < V0) in space()
349 if (pt->position >= V0) { in find_next_trap()
409 else if (v.post > V0) { in output()
473 else if (y < V0) { in space()
474 vertical_position = V0; in space()
[all …]
H A Dcolumn.cpp176 return V0; in distance()
181 return V0; in height()
186 return V0; in extra_space()
232 current = V0; in reset()
283 : bottom(V0), col(0), tail(&col), out(0) in column()
400 bottom = V0; in reset()
421 vunits vpos(V0); in output()
432 bottom = V0; in output()
441 return V0; in get_last_extra_space()
475 if (v <= V0) { in append()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
H A DHexagonCallingConv.td116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
148 CCAssignToReg<[V0]>>>,
156 CCAssignToReg<[V0]>>>,
H A DHexagonISelDAGToDAG.cpp2164 SDValue V0 = L0.Value; in balanceSubTree() local
2170 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
2176 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0); in balanceSubTree()
2182 std::swap(V0, V1); in balanceSubTree()
2187 assert(NodeHeights.count(V0) && NodeHeights.count(V1) && in balanceSubTree()
2189 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1; in balanceSubTree()
2194 ISD::SHL, SDLoc(V0), VT, V0, in balanceSubTree()
2197 TLI.getScalarShiftAmountTy(DL, V0.getValueType()))); in balanceSubTree()
2199 NewNode = CurDAG->getNode(NOpcode, SDLoc(N), VT, V0, V1); in balanceSubTree()
2222 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local
[all …]
/netbsd-src/lib/libm/src/
H A De_j1f.c97 static const float V0[5] = { variable
150 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in __ieee754_y1f()
H A De_j1.c136 static const double V0[5] = { variable
189 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in __ieee754_y1()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp416 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local
417 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1); in foldExtExtCmp()
434 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local
436 Builder.CreateBinOp(cast<BinaryOperator>(&I)->getOpcode(), V0, V1); in foldExtExtBinop()
460 Value *V0, *V1; in foldExtractExtract() local
462 if (!match(I0, m_ExtractElt(m_Value(V0), m_ConstantInt(C0))) || in foldExtractExtract()
464 V0->getType() != V1->getType()) in foldExtractExtract()
585 Value *V0 = nullptr, *V1 = nullptr; in scalarizeBinopOrCmp() local
587 if (!match(Ins0, m_InsertElt(m_Constant(VecC0), m_Value(V0), in scalarizeBinopOrCmp()
596 bool IsConst0 = !V0; in scalarizeBinopOrCmp()
[all …]
/netbsd-src/external/bsd/pcc/dist/pcc/cc/cpp/tests/
H A Dtest1920 #define V0(x)\
33 V0(__COUNTER__)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVECallingConv.td107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp170 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
188 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
208 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
228 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
242 Reg = RISCV::V0; in decodeVMaskReg()
/netbsd-src/external/bsd/pcc/dist/pcc/arch/mips/
H A Dorder.c177 { NRES, V0 }, in nspecial()
197 { NRES, V0 }, in nspecial()
H A Dmacdefs.h140 #define V0 2 macro
230 F0 : V0)
297 { V0, V1, -1 }, /* $v0:$v1 */ \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp470 Constant *V0 = ConstantFP::get(CI->getContext(), APFloat(0.0f)); in generateCondForPow() local
474 V0 = ConstantExpr::getFPExtend(V0, Exp->getType()); in generateCondForPow()
477 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0); in generateCondForPow()
/netbsd-src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/
H A DDarwin.h428 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
431 return TargetVersion < VersionTuple(V0, V1, V2);
438 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
448 : TargetVersion) < VersionTuple(V0, V1, V2);
/netbsd-src/crypto/external/bsd/openssl.old/dist/test/certs/
H A Ddhp2048.pem7 V0/iN2uElrJZIGxD2uPMZNXO+dci+EriMwIBAg==
/netbsd-src/external/gpl3/gcc.old/dist/contrib/
H A Dparanoia.cc989 FLOAT V, V0, V9; member
2134 V0 = V9; in main()
2135 if (V - Y == V + V0) in main()
2151 if (Z < V0) in main()
2153 if (Y < V0) in main()
2155 if (V0 - V < V0) in main()
2156 V = V0; in main()
2165 printf ("Overflow saturates at V0 = %s .\n", V0.str()); in main()
2178 if (!(-V < V && -V0 < V0 && -UfThold < V && UfThold < V)) in main()
2182 V.str(), V0.str(), UfThold.str()); in main()
[all …]
/netbsd-src/external/gpl3/gcc/dist/contrib/
H A Dparanoia.cc989 FLOAT V, V0, V9; member
2134 V0 = V9; in main()
2135 if (V - Y == V + V0) in main()
2151 if (Z < V0) in main()
2153 if (Y < V0) in main()
2155 if (V0 - V < V0) in main()
2156 V = V0; in main()
2165 printf ("Overflow saturates at V0 = %s .\n", V0.str()); in main()
2178 if (!(-V < V && -V0 < V0 && -UfThold < V && UfThold < V)) in main()
2182 V.str(), V0.str(), UfThold.str()); in main()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp324 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
325 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
326 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
327 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
330 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
331 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
332 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1829 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
1830 SDLoc dl(V0.getNode()); in createGPRPairNode()
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
393 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) { in drillValueDownOneStep()
399 Addend0.set(C, V0); in drillValueDownOneStep()
469 Value *V0 = I->getOperand(0); in simplify() local
471 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) && in simplify()
1828 Value *V0, *V1; in visitSub() local
1829 if (match(Op0, m_AddRdx(V0)) && match(Op1, m_AddRdx(V1)) && in visitSub()
1830 V0->getType() == V1->getType()) { in visitSub()
1833 Value *Sub = Builder.CreateSub(V0, V1); in visitSub()
2342 Value *A0, *A1, *V0, *V1; in visitFSub() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td897 // Mask can be V0~V31
991 // Like VPseudoBinaryMask, but output can be V0.
2183 (mask_type V0),
2188 (mask_type V0), GPR:$vl, sew)>;
2206 (mti.Mask V0),
2211 (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
2283 (mask_type V0),
2289 (mask_type V0), GPR:$vl, sew)>;
2306 (mask_type V0),
2312 (mask_type V0), GPR:$vl, sew)>;
[all …]

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