| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 254 Register UseReg; in addLinkerOpt() member
298 Pair.UseReg = BBI->getOperand(0).getReg(); in addLinkerOpt()
316 if (BBI->readsRegister(Pair->UseReg, TRI) || in addLinkerOpt()
317 BBI->modifiesRegister(Pair->UseReg, TRI)) { in addLinkerOpt()
333 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
335 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
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| H A D | PPCVSXSwapRemoval.cpp | 722 Register UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
799 Register UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
800 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTaggingPreRA.cpp | 280 Register UseReg = WorkList.back(); in findFirstSlotCandidate() local
282 for (auto &UseI : MRI->use_instructions(UseReg)) { in findFirstSlotCandidate()
297 << Register::virtReg2Index(UseReg) << " in " << UseI in findFirstSlotCandidate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 250 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
253 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
259 static Register UseReg(const MachineOperand& MO) { in UseReg() function
270 Register I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
337 Register I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 498 Register UseReg, uint8_t OpTy, in getRegSeqInit() argument
500 MachineInstr *Def = MRI.getVRegDef(UseReg); in getRegSeqInit()
555 Register UseReg = OpToFold.getReg(); in tryToFoldACImm() local
556 if (!UseReg.isVirtual()) in tryToFoldACImm()
565 MachineInstr *Def = MRI.getVRegDef(UseReg); in tryToFoldACImm()
577 if (!getRegSeqInit(Defs, UseReg, OpTy, TII, MRI)) in tryToFoldACImm()
743 Register UseReg = OpToFold.getReg(); in foldOperand() local
744 UseMI->getOperand(1).setReg(UseReg); in foldOperand()
756 getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32, TII, in foldOperand()
916 Register UseReg = UseOp.getReg(); in foldOperand() local
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 731 unsigned UseReg = MO.getReg(); in getMachineOpValue() local
755 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { in getMachineOpValue()
774 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); in getMachineOpValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 207 unsigned ARMSelectCallOp(bool UseReg);
2170 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2171 if (UseReg) in ARMSelectCallOp()
2383 bool UseReg = false; in SelectCall() local
2385 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2388 if (UseReg) { in SelectCall()
2398 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2405 if (UseReg) { in SelectCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 909 unsigned UseReg = SubsequentUse->getReg(); in runOnMachineFunction() local
911 if (DefReg != UseReg || !MRI.hasOneUse(DefReg)) in runOnMachineFunction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 400 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
403 let Uses = [UseReg];
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| H A D | MipsInstrInfo.td | 1723 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1726 let Uses = [UseReg];
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