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Searched refs:UndefReg (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anon11f0a5620111::RegSeqInfo
61 UndefReg.push_back(Chan); in RegSeqInfo()
162 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
165 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++])); in tryMergeVector()
192 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
231 RSI->UndefReg = UpdatedUndef; in RebuildVector()
299 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
314 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
H A DSILowerI1Copies.cpp428 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local
430 UndefReg); in insertUndefLaneMask()
431 return UndefReg; in insertUndefLaneMask()
H A DAMDGPUInstructionSelector.cpp2003 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2004 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2008 .addReg(UndefReg) in selectG_SZA_EXT()
2062 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2065 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2069 .addReg(UndefReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp11211 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
11214 UndefReg, Src0, SDValue()); in PostISelFolding()
11228 Src0 = UndefReg; in PostISelFolding()
11229 Src1 = UndefReg; in PostISelFolding()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp543 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
547 .addReg(UndefReg) in adjustCallSequence()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp310 Register UndefReg; in matchCombineShuffleVector() local
314 if (!UndefReg) { in matchCombineShuffleVector()
316 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
318 Ops.push_back(UndefReg); in matchCombineShuffleVector()
2836 Register UndefReg; in applyCombineInsertVecElts() local
2838 if (UndefReg) in applyCombineInsertVecElts()
2839 return UndefReg; in applyCombineInsertVecElts()
2841 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
2842 return UndefReg; in applyCombineInsertVecElts()
H A DLegalizerHelper.cpp1431 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
1433 Unmerges.push_back(UndefReg); in widenScalarMergeValues()