| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 395 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP() local
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
426 unsigned TempReg = createResultReg(RC); in materializeGV() local
427 emitInst(Mips::ADDiu, TempReg) in materializeGV()
430 DestReg = TempReg; in materializeGV()
652 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
653 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
654 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
658 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
659 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 654 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue() local
689 &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg); in emitPrologue()
693 SingleScratchReg = ScratchReg == TempReg; in emitPrologue()
796 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
800 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
811 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
873 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
906 .addDef(TempReg) // TempReg stores the old sp. in emitPrologue()
913 .addReg(TempReg) in emitPrologue()
937 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) in emitPrologue()
[all …]
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| H A D | PPCISelDAGToDAG.cpp | 451 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in getGlobalBaseReg() local
454 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg); in getGlobalBaseReg()
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| H A D | PPCISelLowering.cpp | 11728 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca() local
11729 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
11733 .addReg(TempReg) in emitProbedAlloca()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1264 Register TempReg; in parseMachineFunctionInfo() local
1265 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) { in parseMachineFunctionInfo()
1269 RegVal = TempReg; in parseMachineFunctionInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1588 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP() local
1652 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1661 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1716 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP_64() local
1774 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
1781 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
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| H A D | ARMFastISel.cpp | 2965 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in ARMLowerPICELF() local
2968 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg) in ARMLowerPICELF()
2981 .addReg(TempReg) in ARMLowerPICELF()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2476 unsigned TempReg = Inst.getOperand(1).getReg(); in validateInstruction() local
2477 if (DestReg == TempReg) { in validateInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 3590 unsigned TempReg);
|