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Searched refs:TSFlags (Results 1 – 25 of 107) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h340 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
344 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
348 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
352 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
364 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
368 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
372 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
376 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
380 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
384 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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H A DSIInstrFormats.td145 let TSFlags{0} = SALU;
146 let TSFlags{1} = VALU;
148 let TSFlags{2} = SOP1;
149 let TSFlags{3} = SOP2;
150 let TSFlags{4} = SOPC;
151 let TSFlags{5} = SOPK;
152 let TSFlags{6} = SOPP;
154 let TSFlags{7} = VOP1;
155 let TSFlags{8} = VOP2;
156 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
59 let TSFlags{8-7} = FlagOperandIdx;
60 let TSFlags{9} = HasNativeOperands;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
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H A DSIPostRABundler.cpp107 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
113 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
117 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DR600Defines.h59 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
60 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
83 let TSFlags{9} = isRestrictSlot1AOK;
87 let TSFlags{10} = isPredicated;
89 let TSFlags{11} = isPredicatedFalse;
91 let TSFlags{12} = isPredicatedNew;
93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
97 let TSFlags{14} = isNewValue; // New-value consumer insn.
99 let TSFlags{15} = hasNewValue; // New-value producer insn.
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h102 static inline unsigned getFormat(uint64_t TSFlags) { in getFormat() argument
103 return (TSFlags & InstFormatMask) >> InstFormatShift; in getFormat()
106 static inline VConstraintType getConstraint(uint64_t TSFlags) { in getConstraint() argument
108 ((TSFlags & ConstraintMask) >> ConstraintShift); in getConstraint()
111 static inline VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
112 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
115 static inline bool hasDummyMaskOp(uint64_t TSFlags) { in hasDummyMaskOp() argument
116 return TSFlags & HasDummyMaskOpMask; in hasDummyMaskOp()
119 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { in doesForceTailAgnostic() argument
120 return TSFlags & ForceTailAgnosticMask; in doesForceTailAgnostic()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp79 uint64_t TSFlags, bool HasREX, uint64_t StartByte,
120 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
121 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
124 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isDispOrCDisp8()
143 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
144 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
145 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
147 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
258 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) in isPCRel32Branch()
380 uint64_t TSFlags, bool HasREX, in emitMemModRMByte() argument
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H A DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
142 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
152 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
153 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
164 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
165 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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H A DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
160 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
162 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
163 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
166 if (Desc.TSFlags & X86II::VEX_W) in printVecCompareInstr()
173 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
174 NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; in printVecCompareInstr()
175 else if (Desc.TSFlags & X86II::VEX_L) in printVecCompareInstr()
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H A DX86BaseInfo.h965 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
966 return (TSFlags & X86II::FormMask) == PrefixByte; in isPrefix()
970 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
971 return (TSFlags & X86II::FormMask) == Pseudo; in isPseudo()
976 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
977 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
980 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
981 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
986 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
987 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
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H A DX86InstPrinterCommon.cpp336 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
339 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
342 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
351 if ((Flags & X86::IP_USE_VEX) || (TSFlags & X86II::ExplicitVEXPrefix)) in printInstFlags()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
H A DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp236 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
243 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
311 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
329 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
335 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
341 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
399 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
418 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
508 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp129 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
132 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
133 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX || in getFMA3Group()
134 (TSFlags & X86II::EncodingMask) == X86II::EVEX) && in getFMA3Group()
135 (TSFlags & X86II::OpMapMask) == X86II::T8 && in getFMA3Group()
136 (TSFlags & X86II::OpPrefixMask) == X86II::PD && in getFMA3Group()
146 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
148 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86EvexToVex.cpp225 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEvexToVexImpl()
231 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) in CompressEvexToVexImpl()
236 if (Desc.TSFlags & X86II::EVEX_L2) in CompressEvexToVexImpl()
253 (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable) in CompressEvexToVexImpl()
H A DX86InstrFormats.td357 // TSFlags layout should be kept in sync with X86BaseInfo.h.
358 let TSFlags{6-0} = FormBits;
359 let TSFlags{8-7} = OpSizeBits;
360 let TSFlags{10-9} = AdSizeBits;
362 let TSFlags{12-11} = OpPrefixBits{1-0};
363 let TSFlags{15-13} = OpMapBits;
364 let TSFlags{16} = hasREX_WPrefix;
365 let TSFlags{20-17} = ImmT.Value;
366 let TSFlags{23-21} = FPForm.Value;
367 let TSFlags{24} = hasLockPrefix;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp30 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
51 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
61 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
110 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
111 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
113 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
H A DARMBaseRegisterInfo.cpp514 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in getFrameIndexInstrOffset()
704 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); in isFrameOffsetLegal()
817 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
818 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
819 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
820 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
821 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp150 uint64_t TSFlags = MI->getDesc().TSFlags; in lowerRISCVVMachineInstrToMCInst() local
158 if (RISCVII::hasVLOp(TSFlags) && OpNo == (NumOps - 2)) in lowerRISCVVMachineInstrToMCInst()
160 if (RISCVII::hasSEWOp(TSFlags) && OpNo == (NumOps - 1)) in lowerRISCVVMachineInstrToMCInst()
164 if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1) { in lowerRISCVVMachineInstrToMCInst()
201 if (RISCVII::hasDummyMaskOp(TSFlags)) in lowerRISCVVMachineInstrToMCInst()
H A DRISCVInstrFormats.td158 let TSFlags{4-0} = format.Value;
162 let TSFlags{7-5} = RVVConstraint.Value;
165 let TSFlags{10-8} = VLMul;
168 let TSFlags{11} = HasDummyMask;
171 let TSFlags{12} = ForceTailAgnostic;
174 let TSFlags{13} = HasMergeOp;
177 let TSFlags{14} = HasSEWOp;
180 let TSFlags{15} = HasVLOp;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp142 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
143 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
169 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DLVLGen.cpp44 if (HAS_VLINDEX(MCID.TSFlags)) in getVLIndex()
45 return GET_VLINDEX(MCID.TSFlags); in getVLIndex()

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