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Searched refs:TII (Results 1 – 25 of 440) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp47 const M68kInstrInfo *TII; member in __anonf661051c0111::M68kExpandPseudo
85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in ExpandMI()
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in ExpandMI()
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in ExpandMI()
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in ExpandMI()
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in ExpandMI()
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in ExpandMI()
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in ExpandMI()
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8); in ExpandMI()
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in ExpandMI()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); in runOnMachineFunction() local
81 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
85 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
89 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
93 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
97 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
101 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
105 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
109 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
113 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp49 const SIInstrInfo *TII; member in __anon082413db0111::SIPeepholeSDWA
95 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
96 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
128 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
129 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
136 uint64_t getSrcMods(const SIInstrInfo *TII,
155 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
156 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
176 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
304 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, in getSrcMods() argument
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H A DR600ExpandSpecialInstrs.cpp29 const R600InstrInfo *TII = nullptr; member in __anon60b21a6a0111::R600ExpandSpecialInstrsPass
63 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
66 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
72 TII = ST.getInstrInfo(); in runOnMachineFunction()
74 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
85 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
89 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
92 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
94 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
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H A DSIShrinkInstructions.cpp62 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates() argument
64 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
78 if (TII->isOperandLegal(MI, Src0Idx, &MovSrc)) { in foldImmediates()
105 if (TII->commuteInstruction(MI)) { in foldImmediates()
106 if (foldImmediates(MI, TII, MRI, false)) in foldImmediates()
110 TII->commuteInstruction(MI); in foldImmediates()
117 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand() argument
119 !TII->isInlineConstant(*Src.getParent(), in isKImmOperand()
123 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKUImmOperand() argument
125 !TII->isInlineConstant(*Src.getParent(), in isKUImmOperand()
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H A DSIFoldOperands.cpp82 const SIInstrInfo *TII; member in __anon0f4bd53b0111::SIFoldOperands
150 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, in isInlineConstantIfFolded() argument
154 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
164 const MCInstrDesc &MadDesc = TII->get(NewOpc); in isInlineConstantIfFolded()
165 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); in isInlineConstantIfFolded()
174 static bool frameIndexMayFold(const SIInstrInfo *TII, in frameIndexMayFold() argument
181 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
184 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
202 const SIInstrInfo &TII, in updateOperand() argument
232 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) { in updateOperand()
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H A DGCNDPPCombine.cpp56 const SIInstrInfo *TII; member in __anon5e250bb70111::GCNDPPCombine
119 if (!TII->isVOP3(Op)) { in isShrinkable()
122 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
152 return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32; in getDPPOp()
196 OrigMI.getDebugLoc(), TII->get(DPPOp)) in createDPPInst()
201 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
212 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
226 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
238 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
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H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anonb7fa72980111::R600PacketizerList
67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
79 if (TII->isPredicated(*BI)) in getPreviousVector()
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
89 if (isTrans || TII->isTransOnly(*BI)) { in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); in substitutePV()
145 TII(ST.getInstrInfo()), in R600PacketizerList()
146 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
164 if (TII->isVector(MI)) in isSoloInstruction()
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H A DSILoadStoreOptimizer.cpp161 void setMI(MachineBasicBlock::iterator MI, const SIInstrInfo &TII,
182 const SIInstrInfo *TII = nullptr; member in __anon923e008a0111::SILoadStoreOptimizer
189 const SIInstrInfo &TII,
283 static unsigned getOpcodeWidth(const MachineInstr &MI, const SIInstrInfo &TII) { in getOpcodeWidth() argument
286 if (TII.isMUBUF(Opc)) { in getOpcodeWidth()
290 if (TII.isMIMG(MI)) { in getOpcodeWidth()
292 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
295 if (TII.isMTBUF(Opc)) { in getOpcodeWidth()
322 static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { in getInstClass() argument
325 if (TII.isMUBUF(Opc)) { in getInstClass()
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H A DSIModeRegister.cpp137 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
139 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
141 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
143 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
146 const SIInstrInfo *TII, Status InstrMode);
164 const SIInstrInfo *TII) { in getInstructionMode() argument
165 if (TII->usesFPDPRounding(MI)) { in getInstructionMode()
186 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg() argument
191 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32)) in insertSetreg()
222 const SIInstrInfo *TII) { in processBlockPhase1() argument
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H A DR600EmitClauseMarkers.cpp33 const R600InstrInfo *TII = nullptr; member in __anon7d4128870111::R600EmitClauseMarkers
51 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
54 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
55 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
70 if (TII->isALUInstr(MI.getOpcode())) in isALU()
72 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
118 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4) in SubstituteKCacheBank()
122 TII->getSrcs(MI); in SubstituteKCacheBank()
124 (TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) && in SubstituteKCacheBank()
182 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in canClauseLocalKillFitInClause()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anon7afaa4350111::MipsInstructionSelector
83 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), in MipsInstructionSelector()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
261 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
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H A DMipsBranchExpansion.cpp167 const MipsInstrInfo *TII; member in __anon424f79550111::MipsBranchExpansion
299 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); in initMBBInfo()
337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
338 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
352 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
396 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
468 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
489 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
494 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
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H A DMipsExpandPseudo.cpp38 const MipsInstrInfo *TII; member in __anon7729a9620111::MipsExpandPseudo
145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DPseudoSourceValue.cpp27 PseudoSourceValue::PseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII) in PseudoSourceValue() argument
29 AddressSpace = TII.getAddressSpaceForPseudoSourceKind(Kind); in PseudoSourceValue()
83 unsigned Kind, const TargetInstrInfo &TII) in CallEntryPseudoSourceValue() argument
84 : PseudoSourceValue(Kind, TII) {} in CallEntryPseudoSourceValue()
100 const TargetInstrInfo &TII) in GlobalValuePseudoSourceValue() argument
101 : CallEntryPseudoSourceValue(GlobalValueCallEntry, TII), GV(GV) {} in GlobalValuePseudoSourceValue()
103 const char *ES, const TargetInstrInfo &TII) in ExternalSymbolPseudoSourceValue() argument
104 : CallEntryPseudoSourceValue(ExternalSymbolCallEntry, TII), ES(ES) {} in ExternalSymbolPseudoSourceValue()
108 : TII(TIInfo), in PseudoSourceValueManager()
109 StackPSV(PseudoSourceValue::Stack, TII), in PseudoSourceValueManager()
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H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in replaceRetWithPatchableRet()
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in prependRetWithPatchableExit()
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp33 const RISCVInstrInfo *TII; member in __anon5697444c0111::RISCVExpandAtomicPseudo
66 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
216 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, in doAtomicBinOpExpansion() argument
233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
239 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
242 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
247 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg) in doAtomicBinOpExpansion()
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
256 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in insertMaskedMerge() argument
267 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp57 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
104 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
121 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
129 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
141 const AVRInstrInfo &TII = *STI.getInstrInfo(); in restoreStatusRegister() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anon23aef0430111::ARMInstructionSelector
174 : InstructionSelector(), TII(*STI.getInstrInfo()), in ARMInstructionSelector()
211 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
224 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
232 const ARMBaseInstrInfo &TII, in selectMergeValues() argument
236 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP"); in selectMergeValues()
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
263 const ARMBaseInstrInfo &TII, in selectUnmergeValues() argument
267 assert(TII.getSubtarget().hasVFP2Base() && in selectUnmergeValues()
288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
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H A DARMFrameLowering.cpp242 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
247 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
250 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
255 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
259 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
326 const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
337 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
354 const TargetInstrInfo &TII, in emitAligningInstructions() argument
377 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
382 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
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H A DThumb1FrameLowering.cpp69 const TargetInstrInfo &TII, const DebugLoc &dl, in emitPrologueEpilogueSPUpdate() argument
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
106 const TargetInstrInfo &TII, const DebugLoc &dl, in emitCallSPUpdate() argument
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
117 const Thumb1InstrInfo &TII = in eliminateCallFramePseudoInstr() local
127 unsigned Amount = TII.getFrameSize(Old); in eliminateCallFramePseudoInstr()
137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
140 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp62 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
72 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
83 const TargetInstrInfo &TII, unsigned DRegNum, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededExtSP() argument
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
123 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
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H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
93 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
129 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp45 const MSP430InstrInfo &TII = in emitPrologue() local
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
110 const MSP430InstrInfo &TII = in emitEpilogue() local
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4); in emitEpilogue()
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4); in emitEpilogue()
161 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
189 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in spillCalleeSavedRegisters() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp142 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
190 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
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