| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 621 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
634 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
728 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
729 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| H A D | MachineCopyPropagation.cpp | 436 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
438 SuperRC; SuperRC = *SuperRCI++) in isForwardableRegClassCopy()
439 if (SuperRC->contains(CopySrcReg)) in isForwardableRegClassCopy()
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| H A D | RegAllocGreedy.cpp | 2072 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
2075 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
2078 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
2112 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
2114 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
2123 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
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| H A D | TargetLoweringBase.cpp | 1245 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1247 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1249 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1251 BestRC = SuperRC; in findRepresentativeClass()
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| H A D | MachineVerifier.cpp | 2010 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
2012 if (!SuperRC) { in visitMachineOperand()
2016 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1078 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1079 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1221 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1223 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1275 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local
1277 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
1326 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1329 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1387 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1390 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
[all …]
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| H A D | SIRegisterInfo.h | 204 getCompatibleSubRegClass(const TargetRegisterClass *SuperRC,
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| H A D | SIInstrInfo.h | 65 const TargetRegisterClass *SuperRC,
71 const TargetRegisterClass *SuperRC,
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| H A D | SIRegisterInfo.cpp | 2153 SIRegisterInfo::getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, in getCompatibleSubRegClass() argument
2158 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
2159 return MatchRC && MatchRC->hasSubClassEq(SuperRC) ? MatchRC : nullptr; in getCompatibleSubRegClass()
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| H A D | SIInstrInfo.cpp | 4532 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
4550 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
4565 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
4577 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
4606 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
4607 if (!SuperRC) in isLegalRegOperand()
4610 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
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| H A D | AMDGPUISelDAGToDAG.cpp | 585 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
590 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 2588 const TargetRegisterClass *SuperRC, in computeIndirectRegIndex() argument
2602 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex()
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| H A D | SIISelLowering.cpp | 3635 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
3638 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 594 const TargetRegisterClass *SuperRC = nullptr; in combine() local
596 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
600 SuperRC = &Hexagon::HvxWRRegClass; in combine()
606 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| H A D | HexagonRegisterInfo.cpp | 438 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
439 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 412 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
413 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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