| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 207 unsigned SubReg1; in isProfitableToTransform() local
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
299 unsigned Src1 = 0, SubReg1; in transformInstruction() local
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in transformInstruction()
348 SubReg1 = 0; in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
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| H A D | AArch64ISelLowering.cpp | 16612 SDValue SubReg1 = DAG.getTargetConstant(AArch64::subo64, dl, MVT::i32); in createGPRPairNode() local
16613 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
16660 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
16662 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
16663 SDValue Lo = DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
215 SubReg0 = SubReg1; in commuteInstructionImpl()
233 CommutedMI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1834 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1835 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1845 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1846 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1857 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1867 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1868 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1879 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1882 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
[all …]
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| H A D | ARMISelLowering.cpp | 9764 SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
9765 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 }; in createGPRPairNode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 780 SDValue RC, SubReg0, SubReg1; in Select() local
785 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32); in Select()
789 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
794 N->getOperand(1), SubReg1 }; in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1172 unsigned SubReg1 = MI.getOperand(1).getSubReg(); in commuteInstructionImpl() local
1183 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); in commuteInstructionImpl()
1215 MI.getOperand(2).setSubReg(SubReg1); in commuteInstructionImpl()
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