| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
48 if (!RC.hasSubClassEq(&SubRC)) in verify()
53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
55 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 952 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
953 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
955 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
959 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
2212 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
2215 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2257 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
2258 if (SubRC.Artificial) in inferMatchingSuperRegClass()
2261 if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) in inferMatchingSuperRegClass()
2266 if (SubRC.contains(SSPairs[i].second)) in inferMatchingSuperRegClass()
[all …]
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| H A D | CodeGenRegisters.h | 401 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
402 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| H A D | RISCVCompressInstEmitter.cpp | 164 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
165 return RC.hasSubClass(&SubRC); in validateTypes()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 200 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
201 if (SubRC->isAllocatable()) in getAllocatableClass()
202 return SubRC; in getAllocatableClass()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 205 const TargetRegisterClass *SubRC,
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| H A D | AMDGPUInstructionSelector.h | 91 const TargetRegisterClass &SubRC,
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| H A D | SIInstrInfo.h | 67 const TargetRegisterClass *SubRC) const;
73 const TargetRegisterClass *SubRC) const;
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| H A D | SIInstrInfo.cpp | 3810 const TargetRegisterClass *SubRC = in verifyInstruction() local
3812 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
3814 RC = SubRC; in verifyInstruction()
4534 const TargetRegisterClass *SubRC) in buildExtractSubReg()
4538 Register SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
4567 const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
4578 SubIdx, SubRC); in buildExtractSubRegOrImm()
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| H A D | SIRegisterInfo.cpp | 2154 const TargetRegisterClass *SubRC, in getCompatibleSubRegClass() argument
2158 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx); in getCompatibleSubRegClass()
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| H A D | AMDGPUInstructionSelector.cpp | 233 const TargetRegisterClass &SubRC, in getSubOperand64() argument
238 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
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| H A D | SIISelLowering.cpp | 4057 const TargetRegisterClass *SubRC = in EmitInstrWithCustomInserter() local
4060 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
4062 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 5293 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
5297 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
5303 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
5308 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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