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Searched refs:ShiftedVal (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp212 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
214 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
215 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp867 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
868 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
880 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
881 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1598 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1599 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1600 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1613 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1614 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1615 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3973 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
3977 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3978 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3981 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
3984 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
3985 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
3986 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
3990 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3991 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3997 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12290 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine() local
12293 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0; in performMulCombine()
12294 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal; in performMulCombine()