| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 862 ARM_AM::ShiftOpc ShiftTy; member
872 ARM_AM::ShiftOpc ShiftTy; member
879 ARM_AM::ShiftOpc ShiftTy; member
1449 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
2551 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2562 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
3305 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
3643 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
3656 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 872 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); in PromoteIntRes_MULFIX() local
874 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX()
879 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX()
976 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); in PromoteIntRes_DIVFIX() local
981 DAG.getConstant(Diff, dl, ShiftTy)); in PromoteIntRes_DIVFIX()
986 DAG.getConstant(Diff, dl, ShiftTy)); in PromoteIntRes_DIVFIX()
1382 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG); in PromoteIntRes_XMULO() local
1384 DAG.getConstant(Shift, DL, ShiftTy)); in PromoteIntRes_XMULO()
3466 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_MULFIX() local
3489 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX()
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| H A D | TargetLowering.cpp | 4085 EVT ShiftTy = in SimplifySetCC() local
4094 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC()
4104 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC()
4112 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() local
4123 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
4151 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
8158 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointMul() local
8160 DAG.getConstant(Scale, dl, ShiftTy)); in expandFixedPointMul()
8188 DAG.getConstant(VTSize - 1, dl, ShiftTy)); in expandFixedPointMul()
8255 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointDiv() local
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| H A D | SelectionDAGBuilder.cpp | 3125 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
3129 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
3130 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
3136 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
3143 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
5447 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local
5452 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
5456 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 794 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
806 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
817 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
818 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
824 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
825 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 182 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2763 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2809 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3758 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local
3761 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost()
4063 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local
4066 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
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| H A D | X86ISelLowering.cpp | 45013 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
45014 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
45019 Shift.getConstantOperandAPInt(1) != (ShiftTy.getSizeInBits() - 1)) in foldXorTruncShiftIntoCmp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1853 const LLT ShiftTy = MRI.getType(ShiftReg); in preISelLower() local
1857 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in preISelLower()
1858 if (SrcTy.getSizeInBits() != 32 || ShiftTy.getSizeInBits() != 64) in preISelLower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1660 LLT ShiftTy = SrcTy; in widenScalarExtract() local
1663 ShiftTy = WideTy; in widenScalarExtract()
1667 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
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| H A D | CombinerHelper.cpp | 1913 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local
1914 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
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