| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 27 enum ShiftOpc { enum
44 inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
116 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
413 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
425 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
426 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
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| H A D | ARMMCCodeEmitter.cpp | 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1258 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1296 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1511 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1556 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1665 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
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| H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
804 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
808 MIB.addImm(ShiftOpc); in selectShift()
1060 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
1062 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
1064 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
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| H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
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| H A D | ARMFastISel.cpp | 182 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2690 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2717 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2763 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
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| H A D | ARMISelDAGToDAG.cpp | 83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
527 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
600 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
624 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
746 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
826 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1495 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
3183 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
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| H A D | ARMBaseInstrInfo.cpp | 232 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
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| H A D | ARMISelLowering.cpp | 17830 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitDouble.cpp | 800 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
838 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
855 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
884 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 459 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
862 ARM_AM::ShiftOpc ShiftTy;
872 ARM_AM::ShiftOpc ShiftTy;
879 ARM_AM::ShiftOpc ShiftTy;
3639 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
3653 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
3804 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, in CreateMem()
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
4141 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1482 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1521 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
1914 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2677 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
2679 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT), in tryBitfieldInsertOpFromOr()
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