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Searched refs:ShiftL (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DScaledNumber.h307 int32_t ShiftL = std::min<int32_t>(countLeadingZeros(LDigits), ScaleDiff); in matchScales() local
308 assert(ShiftL < getWidth<DigitsT>() && "can't shift more than width"); in matchScales()
310 int32_t ShiftR = ScaleDiff - ShiftL; in matchScales()
317 LDigits <<= ShiftL; in matchScales()
320 LScale -= ShiftL; in matchScales()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3545 SDValue ShiftL = in get64BitZExtCompare() local
3556 ShiftR, ShiftL, SubtractCarry), 0); in get64BitZExtCompare()
3707 SDValue ShiftL = in get64BitSExtCompare() local
3716 ShiftR, ShiftL, SubtractCarry), 0); in get64BitSExtCompare()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1813 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); in widenScalarAddSubShlSat() local
1817 {ShiftL, ShiftR}, MI.getFlags()); in widenScalarAddSubShlSat()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp17936 SDValue ShiftL = Op; in SimplifyDemandedBitsForTargetNode() local
17941 if (!ShiftL.hasOneUse() || !ShiftR.hasOneUse()) in SimplifyDemandedBitsForTargetNode()
17944 unsigned ShiftLBits = ShiftL->getConstantOperandVal(1); in SimplifyDemandedBitsForTargetNode()