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Searched refs:ShiftAmount (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp66 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeqImpl() local
67 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in generateInstSeqImpl()
71 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl()
86 unsigned ShiftAmount = countLeadingZeros((uint64_t)Val); in generateInstSeq() local
87 Val <<= ShiftAmount; in generateInstSeq()
91 Val |= maskTrailingOnes<uint64_t>(ShiftAmount); in generateInstSeq()
95 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount)); in generateInstSeq()
102 Val &= maskTrailingZeros<uint64_t>(ShiftAmount); in generateInstSeq()
105 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount)); in generateInstSeq()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
344 ShiftAmount -= 4; in LowerShifts()
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
346 ShiftAmount < 7) { in LowerShifts()
351 ShiftAmount -= 4; in LowerShifts()
352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { in LowerShifts()
355 ShiftAmount = 0; in LowerShifts()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp307 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second); in eliminateFrameIndex() local
308 if (ShiftAmount != 0) in eliminateFrameIndex()
311 .addImm(ShiftAmount); in eliminateFrameIndex()
H A DRISCVFrameLowering.cpp499 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
504 .addImm(ShiftAmount); in emitPrologue()
507 .addImm(ShiftAmount); in emitPrologue()
H A DRISCVInstrInfo.cpp1374 uint32_t ShiftAmount = Log2_32(NumOfVReg); in getVLENFactoredAmount() local
1375 if (ShiftAmount == 0) in getVLENFactoredAmount()
1379 .addImm(ShiftAmount); in getVLENFactoredAmount()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h48 unsigned ShiftAmount) const;
H A DMipsSEISelDAGToDAG.cpp283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
H A DMipsTargetStreamer.h145 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp268 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
270 if (ShiftAmount >= 32) { in emitDSLL()
271 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
275 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
H A DMipsMCCodeEmitter.h188 template <unsigned ShiftAmount = 0>
H A DMipsMCCodeEmitter.cpp753 template <unsigned ShiftAmount>
764 OffBits >>= ShiftAmount; in getMemEncoding()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp967 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
972 if (ShiftAmount >= 8) { in LowerShifts()
992 ShiftAmount -= 8; in LowerShifts()
995 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
999 ShiftAmount -= 1; in LowerShifts()
1002 while (ShiftAmount--) in LowerShifts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp391 unsigned ShiftAmount; member
545 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
838 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1884 unsigned ShiftAmount = 0, in CreateReg() argument
1892 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
1903 unsigned ShiftAmount = 0, in CreateVectorReg() argument
1908 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
1948 unsigned ShiftAmount, in CreateShiftedImm() argument
1953 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2725 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp1004 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
1009 ShiftAmount)); in instCombineIntrinsic()
1049 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros(); in instCombineIntrinsic() local
1053 ShiftAmount)); in instCombineIntrinsic()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DValueTracking.cpp6664 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6666 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6670 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
6673 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
6685 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
6687 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
6688 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
6702 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
6703 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
6707 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1043 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1045 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1046 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
H A DTargetLowering.cpp6336 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
6338 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { in expandMUL_LOHI()
6344 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); in expandMUL_LOHI()
7337 SDValue ShiftAmount = in scalarizeVectorLoad() local
7340 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
7422 SDValue ShiftAmount = in scalarizeVectorStore() local
7425 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
7599 SDValue ShiftAmount = in expandUnalignedLoad() local
7602 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
7713 SDValue ShiftAmount = DAG.getConstant( in expandUnalignedStore() local
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H A DLegalizeIntegerTypes.cpp823 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); in PromoteIntRes_ADDSUBSHLSAT() local
825 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
828 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
832 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
3489 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX() local
3491 ShiftAmount); in ExpandIntRes_MULFIX()
3493 ShiftAmount); in ExpandIntRes_MULFIX()
H A DLegalizeDAG.cpp1584 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
1591 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1592 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1594 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1595 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1857 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1858 if (ShiftAmount == Power) in factorOutPowerOf2()
1860 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp498 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
500 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
511 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp460 unsigned &ShiftAmount);
5255 const MCExpr *ShiftAmount; in parsePKHImm() local
5258 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
5262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
5338 const MCExpr *ShiftAmount; in parseShifterImm() local
5340 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
5344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
5400 const MCExpr *ShiftAmount; in parseRotImm() local
5402 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
5406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2392 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
2426 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
2427 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
2434 if (ShlImm - ShiftAmount != 0 && !BiggerPattern) in isBitfieldPositioningOp()
2436 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
H A DAArch64ISelLowering.cpp10963 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1); in shouldReduceLoadWidth() local
10965 if (ShiftAmount == Log2_32(LoadBytes)) in shouldReduceLoadWidth()
12539 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
12551 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
12927 uint64_t ShiftAmount = Shift.getConstantOperandVal(1); in performVectorTruncateCombine() local
12928 if (ShiftAmount != 1) in performVectorTruncateCombine()
13576 int64_t ShiftAmount; in tryCombineShiftImm() local
13586 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
13588 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
13627 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) { in tryCombineShiftImm()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1338 template <unsigned Bits, unsigned ShiftAmount = 0>
1346 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1350 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
2814 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
2815 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; in loadImmediate()
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()

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