Searched refs:Shift1 (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 655 bool Shift1 = mi_match( in selectG_BUILD_VECTOR_TRUNC() local
659 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR_TRUNC()
663 } else if (Shift1) { in selectG_BUILD_VECTOR_TRUNC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1877 Register Shift1 = in applyShiftOfShiftedLogic() local
1887 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 5269 def Shift1 {
5275 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
5276 (AND Shift1.Left, MaskValues.Hi1));
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6190 SDValue Shift1 = N1.getOperand(0); in matchBSwapHWordOrAndAnd() local
6191 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6194 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); in matchBSwapHWordOrAndAnd()
6199 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28380 SDValue Shift1 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
28384 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
42997 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
43001 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
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