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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DScaledNumber.cpp48 int Shift = 64 - LeadingZeros; in multiply64() local
50 Upper = Upper << LeadingZeros | Lower >> Shift; in multiply64()
51 return getRounded(Upper, Shift, in multiply64()
52 Shift && (Lower & UINT64_C(1) << (Shift - 1))); in multiply64()
64 int Shift = 0; in divide32() local
66 Shift -= Zeros; in divide32()
74 return getAdjusted<uint32_t>(Quotient, Shift); in divide32()
77 return getRounded<uint32_t>(Quotient, Shift, Remainder >= getHalf(Divisor)); in divide32()
86 int Shift = 0; in divide64() local
88 Shift -= Zeros; in divide64()
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/frv/
H A Dmcpli.cgs13 mcpli fr8,0x0,fr10 ; Shift by 0
17 mcpli fr8,0x1,fr10 ; Shift by 1
21 mcpli fr8,0x4,fr10 ; Shift by 4
25 mcpli fr8,0xc,fr10 ; Shift by 12
29 mcpli fr8,0x1c,fr10 ; Shift by 28
33 mcpli fr8,0x1f,fr10 ; Shift by 31
38 mcpli fr8,0x20,fr10 ; Shift by 0
42 mcpli fr8,0x21,fr10 ; Shift by 1
46 mcpli fr8,0x24,fr10 ; Shift by 4
50 mcpli fr8,0x2c,fr10 ; Shift by 12
[all …]
H A Dmcplhi.cgs13 mcplhi fr8,0x0,fr10 ; Shift by 0
17 mcplhi fr8,0x1,fr10 ; Shift by 1
21 mcplhi fr8,0x4,fr10 ; Shift by 4
25 mcplhi fr8,0xc,fr10 ; Shift by 12
29 mcplhi fr8,0xf,fr10 ; Shift by 15
34 mcplhi fr8,0x10,fr10 ; Shift by 0
38 mcplhi fr8,0x21,fr10 ; Shift by 1
42 mcplhi fr8,0x34,fr10 ; Shift by 4
46 mcplhi fr8,0x1c,fr10 ; Shift by 12
50 mcplhi fr8,0x2f,fr10 ; Shift by 15
H A Dcsllcc.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dcsll.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dcsrl.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dcsrlcc.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dcsracc.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dcsra.cgs12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
[all …]
H A Dmsllhi.cgs11 msllhi fr8,0x20,fr8 ; Shift by 0
15 msllhi fr8,0,fr8 ; Shift by 0
19 msllhi fr8,1,fr8 ; Shift by 1
23 msllhi fr8,31,fr8 ; Shift by 15
H A Dmsrahi.cgs11 msrahi fr8,0x20,fr8 ; Shift by 0
15 msrahi fr8,0,fr8 ; Shift by 0
19 msrahi fr8,1,fr8 ; Shift by 1
23 msrahi fr8,31,fr8 ; Shift by 15
H A Dmsrlhi.cgs11 msrlhi fr8,0x20,fr8 ; Shift by 0
15 msrlhi fr8,0,fr8 ; Shift by 0
19 msrlhi fr8,1,fr8 ; Shift by 1
23 msrlhi fr8,31,fr8 ; Shift by 15
H A Dmrotli.cgs11 mrotli fr8,0x20,fr8 ; Shift by 0
15 mrotli fr8,0,fr8 ; Shift by 0
19 mrotli fr8,1,fr8 ; Shift by 1
23 mrotli fr8,31,fr8 ; Shift by 31
H A Dmrotri.cgs11 mrotri fr8,0x20,fr8 ; Shift by 0
15 mrotri fr8,0,fr8 ; Shift by 0
19 mrotri fr8,1,fr8 ; Shift by 1
23 mrotri fr8,31,fr8 ; Shift by 31
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp269 unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN in expandMOVImmSimple() local
274 Shift = (TZ / 16) * 16; in expandMOVImmSimple()
277 unsigned Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
280 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
282 if (Shift == LastShift) in expandMOVImmSimple()
291 while (Shift < LastShift) { in expandMOVImmSimple()
292 Shift += 16; in expandMOVImmSimple()
293 Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
298 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
312 for (unsigned Shift = 0; Shift < BitSize; Shift += 16) { in expandMOVImm() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DLEB128.h133 unsigned Shift = 0; variable
145 if ((Shift >= 64 && Slice != 0) || Slice << Shift >> Shift != Slice) {
152 Value += Slice << Shift;
153 Shift += 7;
166 unsigned Shift = 0; variable
180 if ((Shift >= 64 && Slice != (Value < 0 ? 0x7f : 0x00)) ||
181 (Shift == 63 && Slice != 0 && Slice != 0x7f)) {
188 Value |= Slice << Shift;
189 Shift += 7;
193 if (Shift < 64 && (Byte & 0x40))
[all …]
H A DScaledNumber.h88 int Shift = 64 - Width - countLeadingZeros(Digits); variable
89 return getRounded<DigitsT>(Digits >> Shift, Scale + Shift,
90 Digits & (UINT64_C(1) << (Shift - 1)));
623 ScaledNumber &operator<<=(int16_t Shift) {
624 shiftLeft(Shift);
627 ScaledNumber &operator>>=(int16_t Shift) {
628 shiftRight(Shift);
633 void shiftLeft(int32_t Shift);
634 void shiftRight(int32_t Shift);
700 static ScaledNumber adjustToWidth(uint64_t N, int32_t Shift) { in adjustToWidth() argument
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/frv/fr400/
H A Dslass.cgs10 set_gr_immed 0,gr7 ; Shift by 0
17 set_gr_immed 1,gr7 ; Shift by 1
25 set_gr_immed 31,gr7 ; Shift 1 by 31
33 set_gr_immed 31,gr7 ; Shift -1 by 31
41 set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14
49 set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15
57 set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20
65 set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14
73 set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15
81 set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDKernelCodeTInfo.h38 #define PRINTCOMP(GetMacro, Shift) \ argument
41 (int)GetMacro(C.compute_pgm_resource_registers >> Shift); \
43 #define PARSECOMP(SetMacro, Shift) \ argument
48 C.compute_pgm_resource_registers &= ~(SetMacro(0xFFFFFFFFFFFFFFFFULL) << Shift); \
49 C.compute_pgm_resource_registers |= SetMacro(Value) << Shift; \
53 #define COMPPGM(name, aname, GetMacro, SetMacro, Shift) \ argument
54 RECORD(name, aname, PRINTCOMP(GetMacro, Shift), PARSECOMP(SetMacro, Shift))
/netbsd-src/external/apache2/llvm/dist/clang/lib/Format/
H A DWhitespaceManager.cpp268 int Shift = 0; in AlignTokenSequence() local
315 Shift = 0; in AlignTokenSequence()
324 Shift = Column - Changes[i].StartOfTokenColumn; in AlignTokenSequence()
325 Changes[i].Spaces += Shift; in AlignTokenSequence()
361 Changes[i].Spaces += Shift; in AlignTokenSequence()
365 Changes[i].Spaces += Shift; in AlignTokenSequence()
367 assert(Shift >= 0); in AlignTokenSequence()
368 Changes[i].StartOfTokenColumn += Shift; in AlignTokenSequence()
370 Changes[i + 1].PreviousEndOfTokenColumn += Shift; in AlignTokenSequence()
554 int Shift = 0; in AlignMacroSequence() local
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
H A DPointerEmbeddedInt.h44 Shift = sizeof(uintptr_t) * CHAR_BIT - Bits, enumerator
66 Value = static_cast<uintptr_t>(I) << Shift;
74 return static_cast<IntT>(static_cast<intptr_t>(Value) >> Shift);
75 return static_cast<IntT>(Value >> Shift);
97 static constexpr int NumLowBitsAvailable = T::Shift;
H A DBitfields.h166 static constexpr StorageType Mask = BP::Umax << Bitfield::Shift;
173 Packed |= StorageValue << Bitfield::Shift;
179 const StorageType StorageValue = (Packed & Mask) >> Bitfield::Shift;
227 static constexpr unsigned Shift = Offset;
230 static constexpr unsigned LastBit = Shift + Bits - 1;
231 static constexpr unsigned NextBit = Shift + Bits;
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/iwmmxt/
H A Dwsrl.cgs17 # Test Halfword Logical Shift Right
43 # Test Halfword Logical Shift Right by CG register
67 # Test Word Logical Shift Right
93 # Test Word Logical Shift Right by CG register
117 # Test Double Word Logical Shift Right
143 # Test Double Word Logical Shift Right by CG register
H A Dwsra.cgs17 # Test Halfword Arithmetic Shift Right
43 # Test Halfword Arithmetic Shift Right by CG register
67 # Test Word Arithmetic Shift Right
93 # Test Word Arithmetic Shift Right by CG register
117 # Test Double Word Arithmetic Shift Right
143 # Test Double Word Arithmetic Shift Right by CG register
H A Dwsll.cgs17 # Test Halfword Logical Shift Left
43 # Test Halfword Aritc Shift Left by CG register
67 # Test Word Logical Shift Left
93 # Test Word Logical Shift Left by CG register
117 # Test Double Word Logical Shift Left
143 # Test Double Word Logical Shift Left by CG register

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